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mlankhorstrodrigovivi
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drm/i915: Do not rely on wm preservation for ILK watermarks
The original intent was to preserve watermarks as much as possible in intel_pipe_wm.raw_wm, and put the validated ones in intel_pipe_wm.wm. It seems this approach is insufficient and we don't always preserve the raw watermarks, so just use the atomic iterator we're already using to get a const pointer to all bound planes on the crtc. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102373 Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: stable@vger.kernel.org #v4.8+ Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171019151341.4579-1-maarten.lankhorst@linux.intel.com (cherry picked from commit 28283f4) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
1 parent 713946d commit 8777b92

2 files changed

Lines changed: 21 additions & 31 deletions

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drivers/gpu/drm/i915/intel_drv.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -496,7 +496,6 @@ struct intel_crtc_scaler_state {
496496

497497
struct intel_pipe_wm {
498498
struct intel_wm_level wm[5];
499-
struct intel_wm_level raw_wm[5];
500499
uint32_t linetime;
501500
bool fbc_wm_enabled;
502501
bool pipe_enabled;

drivers/gpu/drm/i915/intel_pm.c

Lines changed: 21 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -2716,9 +2716,9 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
27162716
const struct intel_crtc *intel_crtc,
27172717
int level,
27182718
struct intel_crtc_state *cstate,
2719-
struct intel_plane_state *pristate,
2720-
struct intel_plane_state *sprstate,
2721-
struct intel_plane_state *curstate,
2719+
const struct intel_plane_state *pristate,
2720+
const struct intel_plane_state *sprstate,
2721+
const struct intel_plane_state *curstate,
27222722
struct intel_wm_level *result)
27232723
{
27242724
uint16_t pri_latency = dev_priv->wm.pri_latency[level];
@@ -3038,28 +3038,24 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
30383038
struct intel_pipe_wm *pipe_wm;
30393039
struct drm_device *dev = state->dev;
30403040
const struct drm_i915_private *dev_priv = to_i915(dev);
3041-
struct intel_plane *intel_plane;
3042-
struct intel_plane_state *pristate = NULL;
3043-
struct intel_plane_state *sprstate = NULL;
3044-
struct intel_plane_state *curstate = NULL;
3041+
struct drm_plane *plane;
3042+
const struct drm_plane_state *plane_state;
3043+
const struct intel_plane_state *pristate = NULL;
3044+
const struct intel_plane_state *sprstate = NULL;
3045+
const struct intel_plane_state *curstate = NULL;
30453046
int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
30463047
struct ilk_wm_maximums max;
30473048

30483049
pipe_wm = &cstate->wm.ilk.optimal;
30493050

3050-
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3051-
struct intel_plane_state *ps;
3052-
3053-
ps = intel_atomic_get_existing_plane_state(state,
3054-
intel_plane);
3055-
if (!ps)
3056-
continue;
3051+
drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {
3052+
const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
30573053

3058-
if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3054+
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
30593055
pristate = ps;
3060-
else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3056+
else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
30613057
sprstate = ps;
3062-
else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
3058+
else if (plane->type == DRM_PLANE_TYPE_CURSOR)
30633059
curstate = ps;
30643060
}
30653061

@@ -3081,11 +3077,9 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
30813077
if (pipe_wm->sprites_scaled)
30823078
usable_level = 0;
30833079

3084-
ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3085-
pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
3086-
30873080
memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3088-
pipe_wm->wm[0] = pipe_wm->raw_wm[0];
3081+
ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3082+
pristate, sprstate, curstate, &pipe_wm->wm[0]);
30893083

30903084
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
30913085
pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
@@ -3095,8 +3089,8 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
30953089

30963090
ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
30973091

3098-
for (level = 1; level <= max_level; level++) {
3099-
struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
3092+
for (level = 1; level <= usable_level; level++) {
3093+
struct intel_wm_level *wm = &pipe_wm->wm[level];
31003094

31013095
ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
31023096
pristate, sprstate, curstate, wm);
@@ -3106,13 +3100,10 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
31063100
* register maximums since such watermarks are
31073101
* always invalid.
31083102
*/
3109-
if (level > usable_level)
3110-
continue;
3111-
3112-
if (ilk_validate_wm_level(level, &max, wm))
3113-
pipe_wm->wm[level] = *wm;
3114-
else
3115-
usable_level = level;
3103+
if (!ilk_validate_wm_level(level, &max, wm)) {
3104+
memset(wm, 0, sizeof(*wm));
3105+
break;
3106+
}
31163107
}
31173108

31183109
return 0;

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