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Merge branch 'at91-5.4-trunk/base_adc' into linux-5.4-at91
2 parents 156aa8a + 92bb19b commit 7646053

1 file changed

Lines changed: 124 additions & 89 deletions

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drivers/iio/adc/at91-sama5d2_adc.c

Lines changed: 124 additions & 89 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88

99
#include <linux/bitops.h>
1010
#include <linux/clk.h>
11+
#include <linux/delay.h>
1112
#include <linux/dma-mapping.h>
1213
#include <linux/dmaengine.h>
1314
#include <linux/interrupt.h>
@@ -100,6 +101,8 @@
100101
#define AT91_SAMA5D2_IER_YRDY BIT(21)
101102
/* Interrupt Enable Register - TS pressure measurement ready */
102103
#define AT91_SAMA5D2_IER_PRDY BIT(22)
104+
/* Interrupt Enable Register - Data ready */
105+
#define AT91_SAMA5D2_IER_DRDY BIT(24)
103106
/* Interrupt Enable Register - general overrun error */
104107
#define AT91_SAMA5D2_IER_GOVRE BIT(25)
105108
/* Interrupt Enable Register - Pen detect */
@@ -486,6 +489,21 @@ static inline int at91_adc_of_xlate(struct iio_dev *indio_dev,
486489
return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
487490
}
488491

492+
static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev)
493+
{
494+
u32 mask = 0;
495+
u8 bit;
496+
497+
for_each_set_bit(bit, indio_dev->active_scan_mask,
498+
indio_dev->num_channels) {
499+
struct iio_chan_spec const *chan =
500+
at91_adc_chan_get(indio_dev, bit);
501+
mask |= BIT(chan->channel);
502+
}
503+
504+
return mask & GENMASK(11, 0);
505+
}
506+
489507
static void at91_adc_config_emr(struct at91_adc_state *st)
490508
{
491509
/* configure the extended mode register */
@@ -710,7 +728,6 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
710728
struct iio_dev *indio = iio_trigger_get_drvdata(trig);
711729
struct at91_adc_state *st = iio_priv(indio);
712730
u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
713-
u8 bit;
714731

715732
/* clear TRGMOD */
716733
status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
@@ -721,50 +738,6 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
721738
/* set/unset hw trigger */
722739
at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
723740

724-
for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
725-
struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit);
726-
u32 cor;
727-
728-
if (!chan)
729-
continue;
730-
/* these channel types cannot be handled by this trigger */
731-
if (chan->type == IIO_POSITIONRELATIVE ||
732-
chan->type == IIO_PRESSURE)
733-
continue;
734-
735-
if (state) {
736-
cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
737-
738-
if (chan->differential)
739-
cor |= (BIT(chan->channel) |
740-
BIT(chan->channel2)) <<
741-
AT91_SAMA5D2_COR_DIFF_OFFSET;
742-
else
743-
cor &= ~(BIT(chan->channel) <<
744-
AT91_SAMA5D2_COR_DIFF_OFFSET);
745-
746-
at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
747-
}
748-
749-
if (state) {
750-
at91_adc_writel(st, AT91_SAMA5D2_CHER,
751-
BIT(chan->channel));
752-
/* enable irq only if not using DMA */
753-
if (!st->dma_st.dma_chan) {
754-
at91_adc_writel(st, AT91_SAMA5D2_IER,
755-
BIT(chan->channel));
756-
}
757-
} else {
758-
/* disable irq only if not using DMA */
759-
if (!st->dma_st.dma_chan) {
760-
at91_adc_writel(st, AT91_SAMA5D2_IDR,
761-
BIT(chan->channel));
762-
}
763-
at91_adc_writel(st, AT91_SAMA5D2_CHDR,
764-
BIT(chan->channel));
765-
}
766-
}
767-
768741
return 0;
769742
}
770743

@@ -781,6 +754,7 @@ static int at91_adc_reenable_trigger(struct iio_trigger *trig)
781754

782755
/* Needed to ACK the DRDY interruption */
783756
at91_adc_readl(st, AT91_SAMA5D2_LCDR);
757+
784758
return 0;
785759
}
786760

@@ -888,18 +862,37 @@ static int at91_adc_dma_start(struct iio_dev *indio_dev)
888862
return 0;
889863
}
890864

865+
static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio,
866+
struct at91_adc_state *st)
867+
{
868+
/* if using DMA, we do not use our own IRQ (we use DMA-controller) */
869+
if (st->dma_st.dma_chan)
870+
return false;
871+
/* if the trigger is not ours, then it has its own IRQ */
872+
if (iio_trigger_validate_own_device(indio->trig, indio))
873+
return false;
874+
return true;
875+
}
876+
877+
static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev)
878+
{
879+
struct at91_adc_state *st = iio_priv(indio_dev);
880+
881+
return !!bitmap_subset(indio_dev->active_scan_mask,
882+
&st->touch_st.channels_bitmask,
883+
AT91_SAMA5D2_MAX_CHAN_IDX + 1);
884+
}
885+
891886
static int at91_adc_buffer_postenable(struct iio_dev *indio_dev)
892887
{
893888
int ret;
889+
u8 bit;
894890
struct at91_adc_state *st = iio_priv(indio_dev);
895891

896892
/* check if we are enabling triggered buffer or the touchscreen */
897-
if (bitmap_subset(indio_dev->active_scan_mask,
898-
&st->touch_st.channels_bitmask,
899-
AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
900-
/* touchscreen enabling */
893+
if (at91_adc_current_chan_is_touch(indio_dev))
901894
return at91_adc_configure_touch(st, true);
902-
}
895+
903896
/* if we are not in triggered mode, we cannot enable the buffer. */
904897
if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
905898
return -EINVAL;
@@ -911,6 +904,36 @@ static int at91_adc_buffer_postenable(struct iio_dev *indio_dev)
911904
return ret;
912905
}
913906

907+
for_each_set_bit(bit, indio_dev->active_scan_mask,
908+
indio_dev->num_channels) {
909+
struct iio_chan_spec const *chan =
910+
at91_adc_chan_get(indio_dev, bit);
911+
u32 cor;
912+
913+
if (!chan)
914+
continue;
915+
/* these channel types cannot be handled by this trigger */
916+
if (chan->type == IIO_POSITIONRELATIVE ||
917+
chan->type == IIO_PRESSURE)
918+
continue;
919+
920+
cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
921+
922+
if (chan->differential)
923+
cor |= (BIT(chan->channel) | BIT(chan->channel2)) <<
924+
AT91_SAMA5D2_COR_DIFF_OFFSET;
925+
else
926+
cor &= ~(BIT(chan->channel) <<
927+
AT91_SAMA5D2_COR_DIFF_OFFSET);
928+
929+
at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
930+
931+
at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
932+
}
933+
934+
if (at91_adc_buffer_check_use_irq(indio_dev, st))
935+
at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY);
936+
914937
return iio_triggered_buffer_postenable(indio_dev);
915938
}
916939

@@ -921,31 +944,18 @@ static int at91_adc_buffer_predisable(struct iio_dev *indio_dev)
921944
u8 bit;
922945

923946
/* check if we are disabling triggered buffer or the touchscreen */
924-
if (bitmap_subset(indio_dev->active_scan_mask,
925-
&st->touch_st.channels_bitmask,
926-
AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
927-
/* touchscreen disable */
947+
if (at91_adc_current_chan_is_touch(indio_dev))
928948
return at91_adc_configure_touch(st, false);
929-
}
949+
930950
/* if we are not in triggered mode, nothing to do here */
931951
if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
932952
return -EINVAL;
933953

934-
/* continue with the triggered buffer */
935-
ret = iio_triggered_buffer_predisable(indio_dev);
936-
if (ret < 0)
937-
dev_err(&indio_dev->dev, "buffer predisable failed\n");
938-
939-
if (!st->dma_st.dma_chan)
940-
return ret;
941-
942-
/* if we are using DMA we must clear registers and end DMA */
943-
dmaengine_terminate_sync(st->dma_st.dma_chan);
944-
945954
/*
946-
* For each enabled channel we must read the last converted value
955+
* For each enable channel we must disable it in hardware.
956+
* In the case of DMA, we must read the last converted value
947957
* to clear EOC status and not get a possible interrupt later.
948-
* This value is being read by DMA from LCDR anyway
958+
* This value is being read by DMA from LCDR anyway, so it's not lost.
949959
*/
950960
for_each_set_bit(bit, indio_dev->active_scan_mask,
951961
indio_dev->num_channels) {
@@ -958,12 +968,28 @@ static int at91_adc_buffer_predisable(struct iio_dev *indio_dev)
958968
if (chan->type == IIO_POSITIONRELATIVE ||
959969
chan->type == IIO_PRESSURE)
960970
continue;
971+
972+
at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
973+
961974
if (st->dma_st.dma_chan)
962975
at91_adc_readl(st, chan->address);
963976
}
964977

978+
if (at91_adc_buffer_check_use_irq(indio_dev, st))
979+
at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY);
980+
965981
/* read overflow register to clear possible overflow status */
966982
at91_adc_readl(st, AT91_SAMA5D2_OVER);
983+
984+
/* continue with the triggered buffer */
985+
ret = iio_triggered_buffer_predisable(indio_dev);
986+
if (ret < 0)
987+
dev_err(&indio_dev->dev, "buffer predisable failed\n");
988+
989+
/* if we are using DMA we must clear registers and end DMA */
990+
if (st->dma_st.dma_chan)
991+
dmaengine_terminate_sync(st->dma_st.dma_chan);
992+
967993
return ret;
968994
}
969995

@@ -1015,6 +1041,22 @@ static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
10151041
int i = 0;
10161042
int val;
10171043
u8 bit;
1044+
u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev);
1045+
unsigned int timeout = 50;
1046+
1047+
/*
1048+
* Check if the conversion is ready. If not, wait a little bit, and
1049+
* in case of timeout exit with an error.
1050+
*/
1051+
while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask &&
1052+
timeout) {
1053+
usleep_range(50, 100);
1054+
timeout--;
1055+
}
1056+
1057+
/* Cannot read data, not ready. Continue without reporting data */
1058+
if (!timeout)
1059+
return;
10181060

10191061
for_each_set_bit(bit, indio_dev->active_scan_mask,
10201062
indio_dev->num_channels) {
@@ -1102,6 +1144,13 @@ static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
11021144
struct iio_dev *indio_dev = pf->indio_dev;
11031145
struct at91_adc_state *st = iio_priv(indio_dev);
11041146

1147+
/*
1148+
* If it's not our trigger, start a conversion now, as we are
1149+
* actually polling the trigger now.
1150+
*/
1151+
if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
1152+
at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
1153+
11051154
if (st->dma_st.dma_chan)
11061155
at91_adc_trigger_handler_dma(indio_dev);
11071156
else
@@ -1114,20 +1163,9 @@ static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
11141163

11151164
static int at91_adc_buffer_init(struct iio_dev *indio)
11161165
{
1117-
struct at91_adc_state *st = iio_priv(indio);
1118-
1119-
if (st->selected_trig->hw_trig) {
1120-
return devm_iio_triggered_buffer_setup(&indio->dev, indio,
1121-
&iio_pollfunc_store_time,
1122-
&at91_adc_trigger_handler, &at91_buffer_setup_ops);
1123-
}
1124-
/*
1125-
* we need to prepare the buffer ops in case we will get
1126-
* another buffer attached (like a callback buffer for the touchscreen)
1127-
*/
1128-
indio->setup_ops = &at91_buffer_setup_ops;
1129-
1130-
return 0;
1166+
return devm_iio_triggered_buffer_setup(&indio->dev, indio,
1167+
&iio_pollfunc_store_time,
1168+
&at91_adc_trigger_handler, &at91_buffer_setup_ops);
11311169
}
11321170

11331171
static unsigned at91_adc_startup_time(unsigned startup_time_min,
@@ -1281,7 +1319,8 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private)
12811319
status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR);
12821320
status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR);
12831321
status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
1284-
} else if (iio_buffer_enabled(indio) && !st->dma_st.dma_chan) {
1322+
} else if (iio_buffer_enabled(indio) &&
1323+
(status & AT91_SAMA5D2_IER_DRDY)) {
12851324
/* triggered buffer without DMA */
12861325
disable_irq_nosync(irq);
12871326
iio_trigger_poll(indio->trig);
@@ -1901,14 +1940,10 @@ static __maybe_unused int at91_adc_resume(struct device *dev)
19011940
return 0;
19021941

19031942
/* check if we are enabling triggered buffer or the touchscreen */
1904-
if (bitmap_subset(indio_dev->active_scan_mask,
1905-
&st->touch_st.channels_bitmask,
1906-
AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
1907-
/* touchscreen enabling */
1943+
if (at91_adc_current_chan_is_touch(indio_dev))
19081944
return at91_adc_configure_touch(st, true);
1909-
} else {
1945+
else
19101946
return at91_adc_configure_trigger(st->trig, true);
1911-
}
19121947

19131948
/* not needed but more explicit */
19141949
return 0;

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