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net: macb: move the Tx and Rx buffer initialization into a function
This patch moves the Tx and Rx buffer initialization into its own function. This does not modify the behaviour of the driver and will be helpful to convert the driver to phylink. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 file changed

Lines changed: 24 additions & 15 deletions

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drivers/net/ethernet/cadence/macb_main.c

Lines changed: 24 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -388,6 +388,27 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
388388
return status;
389389
}
390390

391+
static void macb_init_buffers(struct macb *bp)
392+
{
393+
struct macb_queue *queue;
394+
unsigned int q;
395+
396+
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
397+
queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
398+
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
399+
if (bp->hw_dma_cap & HW_DMA_CAP_64B)
400+
queue_writel(queue, RBQPH,
401+
upper_32_bits(queue->rx_ring_dma));
402+
#endif
403+
queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
404+
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
405+
if (bp->hw_dma_cap & HW_DMA_CAP_64B)
406+
queue_writel(queue, TBQPH,
407+
upper_32_bits(queue->tx_ring_dma));
408+
#endif
409+
}
410+
}
411+
391412
/**
392413
* macb_set_tx_clk() - Set a clock to a new frequency
393414
* @clk Pointer to the clock to change
@@ -1314,26 +1335,14 @@ static void macb_hresp_error_task(unsigned long data)
13141335
bp->macbgem_ops.mog_init_rings(bp);
13151336

13161337
/* Initialize TX and RX buffers */
1317-
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1318-
queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
1319-
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1320-
if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1321-
queue_writel(queue, RBQPH,
1322-
upper_32_bits(queue->rx_ring_dma));
1323-
#endif
1324-
queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1325-
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1326-
if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1327-
queue_writel(queue, TBQPH,
1328-
upper_32_bits(queue->tx_ring_dma));
1329-
#endif
1338+
macb_init_buffers(bp);
13301339

1331-
/* Enable interrupts */
1340+
/* Enable interrupts */
1341+
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
13321342
queue_writel(queue, IER,
13331343
bp->rx_intr_mask |
13341344
MACB_TX_INT_FLAGS |
13351345
MACB_BIT(HRESP));
1336-
}
13371346

13381347
ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
13391348
macb_writel(bp, NCR, ctrl);

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