@@ -293,10 +293,10 @@ static void mvebu_gpio_irq_ack(struct irq_data *d)
293293{
294294 struct irq_chip_generic * gc = irq_data_get_irq_chip_data (d );
295295 struct mvebu_gpio_chip * mvchip = gc -> private ;
296- u32 mask = ~( 1 << ( d -> irq - gc -> irq_base )) ;
296+ u32 mask = d -> mask ;
297297
298298 irq_gc_lock (gc );
299- writel_relaxed (mask , mvebu_gpioreg_edge_cause (mvchip ));
299+ writel_relaxed (~ mask , mvebu_gpioreg_edge_cause (mvchip ));
300300 irq_gc_unlock (gc );
301301}
302302
@@ -305,7 +305,7 @@ static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
305305 struct irq_chip_generic * gc = irq_data_get_irq_chip_data (d );
306306 struct mvebu_gpio_chip * mvchip = gc -> private ;
307307 struct irq_chip_type * ct = irq_data_get_chip_type (d );
308- u32 mask = 1 << ( d -> irq - gc -> irq_base ) ;
308+ u32 mask = d -> mask ;
309309
310310 irq_gc_lock (gc );
311311 ct -> mask_cache_priv &= ~mask ;
@@ -319,8 +319,7 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
319319 struct irq_chip_generic * gc = irq_data_get_irq_chip_data (d );
320320 struct mvebu_gpio_chip * mvchip = gc -> private ;
321321 struct irq_chip_type * ct = irq_data_get_chip_type (d );
322-
323- u32 mask = 1 << (d -> irq - gc -> irq_base );
322+ u32 mask = d -> mask ;
324323
325324 irq_gc_lock (gc );
326325 ct -> mask_cache_priv |= mask ;
@@ -333,8 +332,7 @@ static void mvebu_gpio_level_irq_mask(struct irq_data *d)
333332 struct irq_chip_generic * gc = irq_data_get_irq_chip_data (d );
334333 struct mvebu_gpio_chip * mvchip = gc -> private ;
335334 struct irq_chip_type * ct = irq_data_get_chip_type (d );
336-
337- u32 mask = 1 << (d -> irq - gc -> irq_base );
335+ u32 mask = d -> mask ;
338336
339337 irq_gc_lock (gc );
340338 ct -> mask_cache_priv &= ~mask ;
@@ -347,8 +345,7 @@ static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
347345 struct irq_chip_generic * gc = irq_data_get_irq_chip_data (d );
348346 struct mvebu_gpio_chip * mvchip = gc -> private ;
349347 struct irq_chip_type * ct = irq_data_get_chip_type (d );
350-
351- u32 mask = 1 << (d -> irq - gc -> irq_base );
348+ u32 mask = d -> mask ;
352349
353350 irq_gc_lock (gc );
354351 ct -> mask_cache_priv |= mask ;
@@ -462,7 +459,7 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
462459 for (i = 0 ; i < mvchip -> chip .ngpio ; i ++ ) {
463460 int irq ;
464461
465- irq = mvchip -> irqbase + i ;
462+ irq = irq_find_mapping ( mvchip -> domain , i ) ;
466463
467464 if (!(cause & (1 << i )))
468465 continue ;
@@ -655,6 +652,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
655652 struct irq_chip_type * ct ;
656653 struct clk * clk ;
657654 unsigned int ngpios ;
655+ bool have_irqs ;
658656 int soc_variant ;
659657 int i , cpu , id ;
660658 int err ;
@@ -665,6 +663,9 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
665663 else
666664 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION ;
667665
666+ /* Some gpio controllers do not provide irq support */
667+ have_irqs = of_irq_count (np ) != 0 ;
668+
668669 mvchip = devm_kzalloc (& pdev -> dev , sizeof (struct mvebu_gpio_chip ),
669670 GFP_KERNEL );
670671 if (!mvchip )
@@ -697,7 +698,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
697698 mvchip -> chip .get = mvebu_gpio_get ;
698699 mvchip -> chip .direction_output = mvebu_gpio_direction_output ;
699700 mvchip -> chip .set = mvebu_gpio_set ;
700- mvchip -> chip .to_irq = mvebu_gpio_to_irq ;
701+ if (have_irqs )
702+ mvchip -> chip .to_irq = mvebu_gpio_to_irq ;
701703 mvchip -> chip .base = id * MVEBU_MAX_GPIO_PER_BANK ;
702704 mvchip -> chip .ngpio = ngpios ;
703705 mvchip -> chip .can_sleep = false;
@@ -758,34 +760,30 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
758760 devm_gpiochip_add_data (& pdev -> dev , & mvchip -> chip , mvchip );
759761
760762 /* Some gpio controllers do not provide irq support */
761- if (!of_irq_count ( np ) )
763+ if (!have_irqs )
762764 return 0 ;
763765
764- /* Setup the interrupt handlers. Each chip can have up to 4
765- * interrupt handlers, with each handler dealing with 8 GPIO
766- * pins. */
767- for (i = 0 ; i < 4 ; i ++ ) {
768- int irq = platform_get_irq (pdev , i );
769-
770- if (irq < 0 )
771- continue ;
772- irq_set_chained_handler_and_data (irq , mvebu_gpio_irq_handler ,
773- mvchip );
774- }
775-
776- mvchip -> irqbase = irq_alloc_descs (-1 , 0 , ngpios , -1 );
777- if (mvchip -> irqbase < 0 ) {
778- dev_err (& pdev -> dev , "no irqs\n" );
779- return mvchip -> irqbase ;
766+ mvchip -> domain =
767+ irq_domain_add_linear (np , ngpios , & irq_generic_chip_ops , NULL );
768+ if (!mvchip -> domain ) {
769+ dev_err (& pdev -> dev , "couldn't allocate irq domain %s (DT).\n" ,
770+ mvchip -> chip .label );
771+ return - ENODEV ;
780772 }
781773
782- gc = irq_alloc_generic_chip ("mvebu_gpio_irq" , 2 , mvchip -> irqbase ,
783- mvchip -> membase , handle_level_irq );
784- if (!gc ) {
785- dev_err (& pdev -> dev , "Cannot allocate generic irq_chip\n" );
786- return - ENOMEM ;
774+ err = irq_alloc_domain_generic_chips (
775+ mvchip -> domain , ngpios , 2 , np -> name , handle_level_irq ,
776+ IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL , 0 , 0 );
777+ if (err ) {
778+ dev_err (& pdev -> dev , "couldn't allocate irq chips %s (DT).\n" ,
779+ mvchip -> chip .label );
780+ goto err_domain ;
787781 }
788782
783+ /* NOTE: The common accessors cannot be used because of the percpu
784+ * access to the mask registers
785+ */
786+ gc = irq_get_domain_generic_chip (mvchip -> domain , 0 );
789787 gc -> private = mvchip ;
790788 ct = & gc -> chip_types [0 ];
791789 ct -> type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW ;
@@ -803,27 +801,23 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
803801 ct -> handler = handle_edge_irq ;
804802 ct -> chip .name = mvchip -> chip .label ;
805803
806- irq_setup_generic_chip (gc , IRQ_MSK (ngpios ), 0 ,
807- IRQ_NOREQUEST , IRQ_LEVEL | IRQ_NOPROBE );
804+ /* Setup the interrupt handlers. Each chip can have up to 4
805+ * interrupt handlers, with each handler dealing with 8 GPIO
806+ * pins.
807+ */
808+ for (i = 0 ; i < 4 ; i ++ ) {
809+ int irq = platform_get_irq (pdev , i );
808810
809- /* Setup irq domain on top of the generic chip. */
810- mvchip -> domain = irq_domain_add_simple (np , mvchip -> chip .ngpio ,
811- mvchip -> irqbase ,
812- & irq_domain_simple_ops ,
813- mvchip );
814- if (!mvchip -> domain ) {
815- dev_err (& pdev -> dev , "couldn't allocate irq domain %s (DT).\n" ,
816- mvchip -> chip .label );
817- err = - ENODEV ;
818- goto err_generic_chip ;
811+ if (irq < 0 )
812+ continue ;
813+ irq_set_chained_handler_and_data (irq , mvebu_gpio_irq_handler ,
814+ mvchip );
819815 }
820816
821817 return 0 ;
822818
823- err_generic_chip :
824- irq_remove_generic_chip (gc , IRQ_MSK (ngpios ), IRQ_NOREQUEST ,
825- IRQ_LEVEL | IRQ_NOPROBE );
826- kfree (gc );
819+ err_domain :
820+ irq_domain_remove (mvchip -> domain );
827821
828822 return err ;
829823}
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