clk: at91: sam9x7: correct the max frequency for qspi gclk

varshini-rajendran · varshini-rajendran · commit 5349329f0483 · 2024-01-27T13:23:37.000+05:30
Correct the max frequency for QSPI GCLK as 200MHz Fixes: d6df2c2 ("clk: at91: sam9x7: add sam9x7 pmc driver") Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
@@ -650,7 +650,7 @@ static const struct {
 	{
 		.n = "qspi_gclk",
 		.id = 35,
-		.r = { .max = 20000000 },
+		.r = { .max = 200000000 },
 		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
 		.pp_mux_table = { 6, 8, },
 		.pp_count = 2,

Original file line number	Diff line number	Diff line change
`@@ -650,7 +650,7 @@ static const struct {`
`650`	`650`	`{`
`651`	`651`	`.n = "qspi_gclk",`
`652`	`652`	`.id = 35,`
`653`		`- .r = { .max = 20000000 },`
	`653`	`+ .r = { .max = 200000000 },`
`654`	`654`	`.pp = { "audiopll_divpmcck", "plla_div2pmcck", },`
`655`	`655`	`.pp_mux_table = { 6, 8, },`
`656`	`656`	`.pp_count = 2,`