spi: atmel-quadspi: Add support for sam9x7 QSPI

- Add support for the sam9x7 QSPI controller in the QSPI driver.
- The sam9x7 QSPI controller does not support pad calibration.
- The data rate supported is upto 100 MHz and the GCK is a 2x clock.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
[durai.manickamkr@microchip.com: logically squashed the commits]
Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>

Author: duraikvddp

drivers/spi/atmel-quadspi.c

@@ -65,6 +65,8 @@
 #define SAMA7G5_QSPI0_MAX_SPEED_HZ	200000000
 #define SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ	133000000
 
+#define SAM9X7_QSPI_MAX_SPEED_HZ	100000000
+
 /* Bitfields in QSPI_CR (Control Register) */
 #define QSPI_CR_QSPIEN                  BIT(0)
 #define QSPI_CR_QSPIDIS                 BIT(1)
@@ -258,11 +260,13 @@ static const struct atmel_qspi_pcal pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE] = {
 
 struct atmel_qspi_caps {
 	u32 max_speed_hz;
+	u32 gclk_freq_hz;
 	bool has_qspick;
 	bool has_gclk;
 	bool has_ricr;
 	bool octal;
 	bool has_dma;
+	bool is_9x7;
 };
 
 struct atmel_qspi_ops;
@@ -1021,11 +1025,17 @@ static int atmel_qspi_set_pad_calibration(struct atmel_qspi *aq)
 	/* DLL On + start calibration. */
 	atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR);
 
-	/* Check synchronization status before updating configuration. */
-	ret =  readl_poll_timeout(aq->regs + QSPI_SR2, val,
-				  (val & QSPI_SR2_DLOCK) &&
-				  !(val & QSPI_SR2_CALBSY), 40,
-				  ATMEL_QSPI_TIMEOUT);
+	/*
+	 * Check synchronization status before updating configuration.
+	 * This synchronization check is not applicable for sam9x7 SOC
+	 * because there is no pad calibration support.
+	 */
+	if (!aq->caps->is_9x7) {
+		ret =  readl_poll_timeout(aq->regs + QSPI_SR2, val,
+				(val & QSPI_SR2_DLOCK) &&
+				!(val & QSPI_SR2_CALBSY), 40,
+				ATMEL_QSPI_TIMEOUT);
+	}
 
 	/* Refresh analogic blocks every 1 ms.*/
 	atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER,
@@ -1057,7 +1067,8 @@ static int atmel_qspi_set_gclk(struct atmel_qspi *aq)
 	else
 		atmel_qspi_write(0, aq, QSPI_DLLCFG);
 
-	ret = clk_set_rate(aq->gclk, aq->slave_max_speed_hz);
+	ret = clk_set_rate(aq->gclk, aq->caps->gclk_freq_hz);
+
 	if (ret) {
 		dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n");
 		return ret;
@@ -1622,17 +1633,28 @@ static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
 
 static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = {
 	.max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ,
+	.gclk_freq_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ,
 	.has_gclk = true,
 	.octal = true,
 	.has_dma = true,
 };
 
 static const struct atmel_qspi_caps atmel_sama7g5_qspi_caps = {
 	.max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ,
+	.gclk_freq_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ,
 	.has_gclk = true,
 	.has_dma = true,
 };
 
+static const struct atmel_qspi_caps atmel_sam9x7_ospi_caps = {
+	.max_speed_hz = SAM9X7_QSPI_MAX_SPEED_HZ,
+	.gclk_freq_hz = 2 * SAM9X7_QSPI_MAX_SPEED_HZ,
+	.has_gclk = true,
+	.octal = true,
+	.has_dma = true,
+	.is_9x7 = true,
+};
+
 static const struct of_device_id atmel_qspi_dt_ids[] = {
 	{
 		.compatible = "atmel,sama5d2-qspi",
@@ -1650,6 +1672,10 @@ static const struct of_device_id atmel_qspi_dt_ids[] = {
 		.compatible = "microchip,sama7g5-qspi",
 		.data = &atmel_sama7g5_qspi_caps,
 	},
+	{
+		.compatible = "microchip,sam9x7-ospi",
+		.data = &atmel_sam9x7_ospi_caps,
+	},
 
 	{ /* sentinel */ }
 };