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Merge tag 'uniphier-fixes-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into fixes
UniPhier ARM SoC fixes for v4.9 - Add "select ARCH_HAS_RESET_CONTROLLER" in Kconfig - Rename wrongly-named mioctrl to sdctrl * tag 'uniphier-fixes-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: change MIO node to SD control node ARM: dts: uniphier: change MIO node to SD control node reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs arm64: uniphier: select ARCH_HAS_RESET_CONTROLLER ARM: uniphier: select ARCH_HAS_RESET_CONTROLLER Signed-off-by: Olof Johansson <olof@lixom.net>
2 parents 2723605 + 8e68c65 commit 10e15a6

7 files changed

Lines changed: 51 additions & 49 deletions

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‎Documentation/devicetree/bindings/reset/uniphier-reset.txt‎

Lines changed: 31 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -6,56 +6,56 @@ System reset
66

77
Required properties:
88
- compatible: should be one of the following:
9-
"socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.
10-
"socionext,uniphier-ld4-reset" - for PH1-LD4 SoC.
11-
"socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.
12-
"socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.
13-
"socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.
14-
"socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.
15-
"socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.
16-
"socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.
9+
"socionext,uniphier-sld3-reset" - for sLD3 SoC.
10+
"socionext,uniphier-ld4-reset" - for LD4 SoC.
11+
"socionext,uniphier-pro4-reset" - for Pro4 SoC.
12+
"socionext,uniphier-sld8-reset" - for sLD8 SoC.
13+
"socionext,uniphier-pro5-reset" - for Pro5 SoC.
14+
"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.
15+
"socionext,uniphier-ld11-reset" - for LD11 SoC.
16+
"socionext,uniphier-ld20-reset" - for LD20 SoC.
1717
- #reset-cells: should be 1.
1818

1919
Example:
2020

2121
sysctrl@61840000 {
22-
compatible = "socionext,uniphier-ld20-sysctrl",
22+
compatible = "socionext,uniphier-ld11-sysctrl",
2323
"simple-mfd", "syscon";
2424
reg = <0x61840000 0x4000>;
2525

2626
reset {
27-
compatible = "socionext,uniphier-ld20-reset";
27+
compatible = "socionext,uniphier-ld11-reset";
2828
#reset-cells = <1>;
2929
};
3030

3131
other nodes ...
3232
};
3333

3434

35-
Media I/O (MIO) reset
36-
---------------------
35+
Media I/O (MIO) reset, SD reset
36+
-------------------------------
3737

3838
Required properties:
3939
- compatible: should be one of the following:
40-
"socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.
41-
"socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC.
42-
"socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.
43-
"socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.
44-
"socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.
45-
"socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.
46-
"socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.
47-
"socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.
40+
"socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.
41+
"socionext,uniphier-ld4-mio-reset" - for LD4 SoC.
42+
"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.
43+
"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.
44+
"socionext,uniphier-pro5-sd-reset" - for Pro5 SoC.
45+
"socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC.
46+
"socionext,uniphier-ld11-mio-reset" - for LD11 SoC.
47+
"socionext,uniphier-ld20-sd-reset" - for LD20 SoC.
4848
- #reset-cells: should be 1.
4949

5050
Example:
5151

5252
mioctrl@59810000 {
53-
compatible = "socionext,uniphier-ld20-mioctrl",
53+
compatible = "socionext,uniphier-ld11-mioctrl",
5454
"simple-mfd", "syscon";
5555
reg = <0x59810000 0x800>;
5656

5757
reset {
58-
compatible = "socionext,uniphier-ld20-mio-reset";
58+
compatible = "socionext,uniphier-ld11-mio-reset";
5959
#reset-cells = <1>;
6060
};
6161

@@ -68,24 +68,24 @@ Peripheral reset
6868

6969
Required properties:
7070
- compatible: should be one of the following:
71-
"socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC.
72-
"socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.
73-
"socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.
74-
"socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.
75-
"socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.
76-
"socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.
77-
"socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.
71+
"socionext,uniphier-ld4-peri-reset" - for LD4 SoC.
72+
"socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.
73+
"socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.
74+
"socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.
75+
"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.
76+
"socionext,uniphier-ld11-peri-reset" - for LD11 SoC.
77+
"socionext,uniphier-ld20-peri-reset" - for LD20 SoC.
7878
- #reset-cells: should be 1.
7979

8080
Example:
8181

8282
perictrl@59820000 {
83-
compatible = "socionext,uniphier-ld20-perictrl",
83+
compatible = "socionext,uniphier-ld11-perictrl",
8484
"simple-mfd", "syscon";
8585
reg = <0x59820000 0x200>;
8686

8787
reset {
88-
compatible = "socionext,uniphier-ld20-peri-reset";
88+
compatible = "socionext,uniphier-ld11-peri-reset";
8989
#reset-cells = <1>;
9090
};
9191

‎arch/arm/boot/dts/uniphier-pro5.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -184,11 +184,11 @@
184184
};
185185

186186
&mio_clk {
187-
compatible = "socionext,uniphier-pro5-mio-clock";
187+
compatible = "socionext,uniphier-pro5-sd-clock";
188188
};
189189

190190
&mio_rst {
191-
compatible = "socionext,uniphier-pro5-mio-reset";
191+
compatible = "socionext,uniphier-pro5-sd-reset";
192192
};
193193

194194
&peri_clk {

‎arch/arm/boot/dts/uniphier-pxs2.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -197,11 +197,11 @@
197197
};
198198

199199
&mio_clk {
200-
compatible = "socionext,uniphier-pxs2-mio-clock";
200+
compatible = "socionext,uniphier-pxs2-sd-clock";
201201
};
202202

203203
&mio_rst {
204-
compatible = "socionext,uniphier-pxs2-mio-reset";
204+
compatible = "socionext,uniphier-pxs2-sd-reset";
205205
};
206206

207207
&peri_clk {

‎arch/arm/mach-uniphier/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
config ARCH_UNIPHIER
22
bool "Socionext UniPhier SoCs"
33
depends on ARCH_MULTI_V7
4+
select ARCH_HAS_RESET_CONTROLLER
45
select ARM_AMBA
56
select ARM_GLOBAL_TIMER
67
select ARM_GIC

‎arch/arm64/Kconfig.platforms‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -190,6 +190,7 @@ config ARCH_THUNDER
190190

191191
config ARCH_UNIPHIER
192192
bool "Socionext UniPhier SoC Family"
193+
select ARCH_HAS_RESET_CONTROLLER
193194
select PINCTRL
194195
help
195196
This enables support for Socionext UniPhier SoC family.

‎arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -257,18 +257,18 @@
257257
reg = <0x59801000 0x400>;
258258
};
259259

260-
mioctrl@59810000 {
261-
compatible = "socionext,uniphier-mioctrl",
260+
sdctrl@59810000 {
261+
compatible = "socionext,uniphier-ld20-sdctrl",
262262
"simple-mfd", "syscon";
263263
reg = <0x59810000 0x800>;
264264

265-
mio_clk: clock {
266-
compatible = "socionext,uniphier-ld20-mio-clock";
265+
sd_clk: clock {
266+
compatible = "socionext,uniphier-ld20-sd-clock";
267267
#clock-cells = <1>;
268268
};
269269

270-
mio_rst: reset {
271-
compatible = "socionext,uniphier-ld20-mio-reset";
270+
sd_rst: reset {
271+
compatible = "socionext,uniphier-ld20-sd-reset";
272272
#reset-cells = <1>;
273273
};
274274
};

‎drivers/reset/reset-uniphier.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@ const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = {
154154
UNIPHIER_RESET_END,
155155
};
156156

157-
const struct uniphier_reset_data uniphier_pro5_mio_reset_data[] = {
157+
const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
158158
UNIPHIER_MIO_RESET_SD(0, 0),
159159
UNIPHIER_MIO_RESET_SD(1, 1),
160160
UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
@@ -360,7 +360,7 @@ static const struct of_device_id uniphier_reset_match[] = {
360360
.compatible = "socionext,uniphier-ld20-reset",
361361
.data = uniphier_ld20_sys_reset_data,
362362
},
363-
/* Media I/O reset */
363+
/* Media I/O reset, SD reset */
364364
{
365365
.compatible = "socionext,uniphier-sld3-mio-reset",
366366
.data = uniphier_sld3_mio_reset_data,
@@ -378,20 +378,20 @@ static const struct of_device_id uniphier_reset_match[] = {
378378
.data = uniphier_sld3_mio_reset_data,
379379
},
380380
{
381-
.compatible = "socionext,uniphier-pro5-mio-reset",
382-
.data = uniphier_pro5_mio_reset_data,
381+
.compatible = "socionext,uniphier-pro5-sd-reset",
382+
.data = uniphier_pro5_sd_reset_data,
383383
},
384384
{
385-
.compatible = "socionext,uniphier-pxs2-mio-reset",
386-
.data = uniphier_pro5_mio_reset_data,
385+
.compatible = "socionext,uniphier-pxs2-sd-reset",
386+
.data = uniphier_pro5_sd_reset_data,
387387
},
388388
{
389389
.compatible = "socionext,uniphier-ld11-mio-reset",
390390
.data = uniphier_sld3_mio_reset_data,
391391
},
392392
{
393-
.compatible = "socionext,uniphier-ld20-mio-reset",
394-
.data = uniphier_pro5_mio_reset_data,
393+
.compatible = "socionext,uniphier-ld20-sd-reset",
394+
.data = uniphier_pro5_sd_reset_data,
395395
},
396396
/* Peripheral reset */
397397
{

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