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Merge tag 'renesas-clk-fixes-for-v7.0-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-fixes
Pull Renesas clk driver fixes from Geert Uytterhoeven: - Fix ordering of module clocks arrays on Renesas RZ/V2H(P) and RZ/V2N - Remove clocks for watchdogs meant for other CPU cores on the Renesas RZ/V2H(P) SoC * tag 'renesas-clk-fixes-for-v7.0-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a09g057: Remove entries for WDT{0,2,3} clk: renesas: r9a09g056: Fix ordering of module clocks array clk: renesas: r9a09g057: Fix ordering of module clocks array
2 parents c369299 + 1b4f047 commit e7a45de

2 files changed

Lines changed: 38 additions & 53 deletions

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‎drivers/clk/renesas/r9a09g056-cpg.c‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -289,6 +289,24 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
289289
BUS_MSTOP(5, BIT(13))),
290290
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
291291
BUS_MSTOP(5, BIT(13))),
292+
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
293+
BUS_MSTOP(11, BIT(0))),
294+
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
295+
BUS_MSTOP(11, BIT(0))),
296+
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
297+
BUS_MSTOP(11, BIT(0))),
298+
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
299+
BUS_MSTOP(11, BIT(1))),
300+
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
301+
BUS_MSTOP(11, BIT(1))),
302+
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
303+
BUS_MSTOP(11, BIT(1))),
304+
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
305+
BUS_MSTOP(11, BIT(2))),
306+
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
307+
BUS_MSTOP(11, BIT(2))),
308+
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
309+
BUS_MSTOP(11, BIT(2))),
292310
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
293311
BUS_MSTOP(11, BIT(3))),
294312
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
@@ -389,24 +407,6 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
389407
BUS_MSTOP(11, BIT(12))),
390408
DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
391409
BUS_MSTOP(11, BIT(12))),
392-
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
393-
BUS_MSTOP(11, BIT(0))),
394-
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
395-
BUS_MSTOP(11, BIT(0))),
396-
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
397-
BUS_MSTOP(11, BIT(0))),
398-
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
399-
BUS_MSTOP(11, BIT(1))),
400-
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
401-
BUS_MSTOP(11, BIT(1))),
402-
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
403-
BUS_MSTOP(11, BIT(1))),
404-
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
405-
BUS_MSTOP(11, BIT(2))),
406-
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
407-
BUS_MSTOP(11, BIT(2))),
408-
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
409-
BUS_MSTOP(11, BIT(2))),
410410
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
411411
BUS_MSTOP(3, BIT(14))),
412412
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,

‎drivers/clk/renesas/r9a09g057-cpg.c‎

Lines changed: 20 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -280,22 +280,30 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
280280
BUS_MSTOP(11, BIT(15))),
281281
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
282282
BUS_MSTOP(12, BIT(0))),
283-
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
284-
BUS_MSTOP(3, BIT(10))),
285-
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
286-
BUS_MSTOP(3, BIT(10))),
287283
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
288284
BUS_MSTOP(1, BIT(0))),
289285
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
290286
BUS_MSTOP(1, BIT(0))),
291-
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
292-
BUS_MSTOP(5, BIT(12))),
293-
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
294-
BUS_MSTOP(5, BIT(12))),
295-
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
296-
BUS_MSTOP(5, BIT(13))),
297-
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
298-
BUS_MSTOP(5, BIT(13))),
287+
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
288+
BUS_MSTOP(3, BIT(11) | BIT(12))),
289+
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
290+
BUS_MSTOP(11, BIT(0))),
291+
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
292+
BUS_MSTOP(11, BIT(0))),
293+
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
294+
BUS_MSTOP(11, BIT(0))),
295+
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
296+
BUS_MSTOP(11, BIT(1))),
297+
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
298+
BUS_MSTOP(11, BIT(1))),
299+
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
300+
BUS_MSTOP(11, BIT(1))),
301+
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
302+
BUS_MSTOP(11, BIT(2))),
303+
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
304+
BUS_MSTOP(11, BIT(2))),
305+
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
306+
BUS_MSTOP(11, BIT(2))),
299307
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
300308
BUS_MSTOP(11, BIT(3))),
301309
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
@@ -396,26 +404,6 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
396404
BUS_MSTOP(11, BIT(12))),
397405
DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
398406
BUS_MSTOP(11, BIT(12))),
399-
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
400-
BUS_MSTOP(3, BIT(11) | BIT(12))),
401-
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
402-
BUS_MSTOP(11, BIT(0))),
403-
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
404-
BUS_MSTOP(11, BIT(0))),
405-
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
406-
BUS_MSTOP(11, BIT(0))),
407-
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
408-
BUS_MSTOP(11, BIT(1))),
409-
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
410-
BUS_MSTOP(11, BIT(1))),
411-
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
412-
BUS_MSTOP(11, BIT(1))),
413-
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
414-
BUS_MSTOP(11, BIT(2))),
415-
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
416-
BUS_MSTOP(11, BIT(2))),
417-
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
418-
BUS_MSTOP(11, BIT(2))),
419407
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
420408
BUS_MSTOP(3, BIT(14))),
421409
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
@@ -598,10 +586,7 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
598586
DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
599587
DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
600588
DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
601-
DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
602589
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
603-
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
604-
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
605590
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
606591
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
607592
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */

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