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drm/i915/dp: Factor out compute_max_compressed_bpp_x16()
Factor out compute_max_compressed_bpp_x16() also used during mode validation in a follow-up change. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-12-imre.deak@intel.com
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1 file changed

Lines changed: 49 additions & 33 deletions

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drivers/gpu/drm/i915/display/intel_dp.c

Lines changed: 49 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -2663,6 +2663,48 @@ static int compute_min_compressed_bpp_x16(struct intel_connector *connector,
26632663
return min_bpp_x16;
26642664
}
26652665

2666+
static int compute_max_compressed_bpp_x16(struct intel_connector *connector,
2667+
int mode_clock, int mode_hdisplay,
2668+
int num_joined_pipes,
2669+
enum intel_output_format output_format,
2670+
int pipe_max_bpp, int max_link_bpp_x16)
2671+
{
2672+
struct intel_display *display = to_intel_display(connector);
2673+
struct intel_dp *intel_dp = intel_attached_dp(connector);
2674+
int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2675+
int throughput_max_bpp_x16;
2676+
int joiner_max_bpp;
2677+
2678+
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2679+
joiner_max_bpp = get_max_compressed_bpp_with_joiner(display,
2680+
mode_clock,
2681+
mode_hdisplay,
2682+
num_joined_pipes);
2683+
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2684+
output_format,
2685+
pipe_max_bpp / 3);
2686+
dsc_max_bpp = min(dsc_sink_max_bpp, dsc_src_max_bpp);
2687+
dsc_max_bpp = min(dsc_max_bpp, joiner_max_bpp);
2688+
2689+
max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
2690+
2691+
throughput_max_bpp_x16 = dsc_throughput_quirk_max_bpp_x16(connector,
2692+
mode_clock);
2693+
if (throughput_max_bpp_x16 < max_link_bpp_x16) {
2694+
max_link_bpp_x16 = throughput_max_bpp_x16;
2695+
2696+
drm_dbg_kms(display->drm,
2697+
"[CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
2698+
connector->base.base.id, connector->base.name,
2699+
FXP_Q4_ARGS(max_link_bpp_x16));
2700+
}
2701+
2702+
max_link_bpp_x16 = align_max_compressed_bpp_x16(connector, output_format,
2703+
pipe_max_bpp, max_link_bpp_x16);
2704+
2705+
return max_link_bpp_x16;
2706+
}
2707+
26662708
/*
26672709
* Calculate the output link min, max bpp values in limits based on the pipe bpp
26682710
* range, crtc_state and dsc mode. Return true on success.
@@ -2692,43 +2734,17 @@ intel_dp_compute_config_link_bpp_limits(struct intel_connector *connector,
26922734

26932735
limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
26942736
} else {
2695-
int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2696-
int throughput_max_bpp_x16;
2697-
int joiner_max_bpp;
26982737
limits->link.min_bpp_x16 =
26992738
compute_min_compressed_bpp_x16(connector, crtc_state->output_format);
27002739

2701-
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2702-
joiner_max_bpp =
2703-
get_max_compressed_bpp_with_joiner(display,
2704-
adjusted_mode->crtc_clock,
2705-
adjusted_mode->hdisplay,
2706-
intel_crtc_num_joined_pipes(crtc_state));
2707-
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2708-
crtc_state->output_format,
2709-
limits->pipe.max_bpp / 3);
2710-
dsc_max_bpp = min(dsc_sink_max_bpp, dsc_src_max_bpp);
2711-
dsc_max_bpp = min(dsc_max_bpp, joiner_max_bpp);
2712-
2713-
max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
2714-
2715-
throughput_max_bpp_x16 =
2716-
dsc_throughput_quirk_max_bpp_x16(connector, adjusted_mode->crtc_clock);
2717-
if (throughput_max_bpp_x16 < max_link_bpp_x16) {
2718-
max_link_bpp_x16 = throughput_max_bpp_x16;
2719-
2720-
drm_dbg_kms(display->drm,
2721-
"[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
2722-
crtc->base.base.id, crtc->base.name,
2723-
connector->base.base.id, connector->base.name,
2724-
FXP_Q4_ARGS(max_link_bpp_x16));
2725-
}
2726-
27272740
max_link_bpp_x16 =
2728-
align_max_compressed_bpp_x16(connector,
2729-
crtc_state->output_format,
2730-
limits->pipe.max_bpp,
2731-
max_link_bpp_x16);
2741+
compute_max_compressed_bpp_x16(connector,
2742+
adjusted_mode->crtc_clock,
2743+
adjusted_mode->hdisplay,
2744+
intel_crtc_num_joined_pipes(crtc_state),
2745+
crtc_state->output_format,
2746+
limits->pipe.max_bpp,
2747+
max_link_bpp_x16);
27322748
}
27332749

27342750
limits->link.max_bpp_x16 = max_link_bpp_x16;

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