Skip to content

Commit e2dcc24

Browse files
krzkkrzk
committed
Merge tag 'renesas-fixes-for-v7.0-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
Renesas fixes for v7.0 - Fix SD card initialization on the RZ/T2H and RZ/N2H EVK boards, - Remove WDT nodes meant for other CPU cores on the RZ/V2H(P) SoC, - Fix Clock Pulse Generator registers on the RZ/T2H and RZ/N2H SoCs, - Fix Versa3-related boot hangs on the RZ/G3S SoM, - Fix Extended SPI interrupts on the R-Car X5H SoC. * tag 'renesas-fixes-for-v7.0-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r8a78000: Fix out-of-range SPI interrupt numbers arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2 arm64: dts: renesas: r9a09g087: Fix CPG register region sizes arm64: dts: renesas: r9a09g077: Fix CPG register region sizes arm64: dts: renesas: r9a09g057: Remove wdt{0,2,3} nodes arm64: dts: renesas: rzv2-evk-cn15-sd: Add ramp delay for SD0 regulator arm64: dts: renesas: rzt2h-n2h-evk: Add ramp delay for SD0 card regulator Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2 parents 22e6afd + 85c2601 commit e2dcc24

7 files changed

Lines changed: 15 additions & 43 deletions

File tree

‎arch/arm64/boot/dts/renesas/r8a78000.dtsi‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -698,7 +698,7 @@
698698
compatible = "renesas,scif-r8a78000",
699699
"renesas,rcar-gen5-scif", "renesas,scif";
700700
reg = <0 0xc0700000 0 0x40>;
701-
interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
701+
interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;
702702
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
703703
clock-names = "fck", "brg_int", "scif_clk";
704704
status = "disabled";
@@ -708,7 +708,7 @@
708708
compatible = "renesas,scif-r8a78000",
709709
"renesas,rcar-gen5-scif", "renesas,scif";
710710
reg = <0 0xc0704000 0 0x40>;
711-
interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
711+
interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;
712712
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
713713
clock-names = "fck", "brg_int", "scif_clk";
714714
status = "disabled";
@@ -718,7 +718,7 @@
718718
compatible = "renesas,scif-r8a78000",
719719
"renesas,rcar-gen5-scif", "renesas,scif";
720720
reg = <0 0xc0708000 0 0x40>;
721-
interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;
721+
interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;
722722
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
723723
clock-names = "fck", "brg_int", "scif_clk";
724724
status = "disabled";
@@ -728,7 +728,7 @@
728728
compatible = "renesas,scif-r8a78000",
729729
"renesas,rcar-gen5-scif", "renesas,scif";
730730
reg = <0 0xc070c000 0 0x40>;
731-
interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;
731+
interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;
732732
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
733733
clock-names = "fck", "brg_int", "scif_clk";
734734
status = "disabled";
@@ -738,7 +738,7 @@
738738
compatible = "renesas,hscif-r8a78000",
739739
"renesas,rcar-gen5-hscif", "renesas,hscif";
740740
reg = <0 0xc0710000 0 0x60>;
741-
interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
741+
interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;
742742
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
743743
clock-names = "fck", "brg_int", "scif_clk";
744744
status = "disabled";
@@ -748,7 +748,7 @@
748748
compatible = "renesas,hscif-r8a78000",
749749
"renesas,rcar-gen5-hscif", "renesas,hscif";
750750
reg = <0 0xc0714000 0 0x60>;
751-
interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;
751+
interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;
752752
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
753753
clock-names = "fck", "brg_int", "scif_clk";
754754
status = "disabled";
@@ -758,7 +758,7 @@
758758
compatible = "renesas,hscif-r8a78000",
759759
"renesas,rcar-gen5-hscif", "renesas,hscif";
760760
reg = <0 0xc0718000 0 0x60>;
761-
interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;
761+
interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;
762762
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
763763
clock-names = "fck", "brg_int", "scif_clk";
764764
status = "disabled";
@@ -768,7 +768,7 @@
768768
compatible = "renesas,hscif-r8a78000",
769769
"renesas,rcar-gen5-hscif", "renesas,hscif";
770770
reg = <0 0xc071c000 0 0x60>;
771-
interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;
771+
interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;
772772
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
773773
clock-names = "fck", "brg_int", "scif_clk";
774774
status = "disabled";

‎arch/arm64/boot/dts/renesas/r9a09g057.dtsi‎

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -581,16 +581,6 @@
581581
status = "disabled";
582582
};
583583

584-
wdt0: watchdog@11c00400 {
585-
compatible = "renesas,r9a09g057-wdt";
586-
reg = <0 0x11c00400 0 0x400>;
587-
clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
588-
clock-names = "pclk", "oscclk";
589-
resets = <&cpg 0x75>;
590-
power-domains = <&cpg>;
591-
status = "disabled";
592-
};
593-
594584
wdt1: watchdog@14400000 {
595585
compatible = "renesas,r9a09g057-wdt";
596586
reg = <0 0x14400000 0 0x400>;
@@ -601,26 +591,6 @@
601591
status = "disabled";
602592
};
603593

604-
wdt2: watchdog@13000000 {
605-
compatible = "renesas,r9a09g057-wdt";
606-
reg = <0 0x13000000 0 0x400>;
607-
clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
608-
clock-names = "pclk", "oscclk";
609-
resets = <&cpg 0x77>;
610-
power-domains = <&cpg>;
611-
status = "disabled";
612-
};
613-
614-
wdt3: watchdog@13000400 {
615-
compatible = "renesas,r9a09g057-wdt";
616-
reg = <0 0x13000400 0 0x400>;
617-
clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
618-
clock-names = "pclk", "oscclk";
619-
resets = <&cpg 0x78>;
620-
power-domains = <&cpg>;
621-
status = "disabled";
622-
};
623-
624594
rtc: rtc@11c00800 {
625595
compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
626596
reg = <0 0x11c00800 0 0x400>;

‎arch/arm64/boot/dts/renesas/r9a09g077.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -974,8 +974,8 @@
974974

975975
cpg: clock-controller@80280000 {
976976
compatible = "renesas,r9a09g077-cpg-mssr";
977-
reg = <0 0x80280000 0 0x1000>,
978-
<0 0x81280000 0 0x9000>;
977+
reg = <0 0x80280000 0 0x10000>,
978+
<0 0x81280000 0 0x10000>;
979979
clocks = <&extal_clk>;
980980
clock-names = "extal";
981981
#clock-cells = <2>;

‎arch/arm64/boot/dts/renesas/r9a09g087.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -977,8 +977,8 @@
977977

978978
cpg: clock-controller@80280000 {
979979
compatible = "renesas,r9a09g087-cpg-mssr";
980-
reg = <0 0x80280000 0 0x1000>,
981-
<0 0x81280000 0 0x9000>;
980+
reg = <0 0x80280000 0 0x10000>,
981+
<0 0x81280000 0 0x10000>;
982982
clocks = <&extal_clk>;
983983
clock-names = "extal";
984984
#clock-cells = <2>;

‎arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@
162162
<100000000>;
163163
renesas,settings = [
164164
80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
165-
00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
165+
00 40 00 00 00 00 00 00 06 0c 19 02 3b f0 90 86
166166
a0 80 30 30 9c
167167
];
168168
};

‎arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,7 @@
5353
regulator-max-microvolt = <3300000>;
5454
gpios-states = <0>;
5555
states = <3300000 0>, <1800000 1>;
56+
regulator-ramp-delay = <60>;
5657
};
5758
#endif
5859

‎arch/arm64/boot/dts/renesas/rzv2-evk-cn15-sd.dtso‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@
2525
regulator-max-microvolt = <3300000>;
2626
gpios-states = <0>;
2727
states = <3300000 0>, <1800000 1>;
28+
regulator-ramp-delay = <60>;
2829
};
2930
};
3031

0 commit comments

Comments
 (0)