Skip to content

Commit dd03650

Browse files
airliedairlied
committed
Merge tag 'amd-drm-fixes-7.0-2026-03-12' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-7.0-2026-03-12: amdgpu: - SMU13 fix - SMU14 fix - Fixes for bringup hw testing - Kerneldoc fix - GC12 idle power fix for compute workloads - DCCG fixes amdkfd: - Fix missing BO unreserve in an error path Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260312180351.3874990-1-alexander.deucher@amd.com
2 parents 8c835a1 + 3646ff2 commit dd03650

13 files changed

Lines changed: 73 additions & 19 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2690,8 +2690,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
26902690
break;
26912691
default:
26922692
r = amdgpu_discovery_set_ip_blocks(adev);
2693-
if (r)
2693+
if (r) {
2694+
adev->num_ip_blocks = 0;
26942695
return r;
2696+
}
26952697
break;
26962698
}
26972699

@@ -3247,6 +3249,8 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
32473249
i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
32483250
if (!adev->ip_blocks[i].status.late_initialized)
32493251
continue;
3252+
if (!adev->ip_blocks[i].version)
3253+
continue;
32503254
/* skip CG for GFX, SDMA on S0ix */
32513255
if (adev->in_s0ix &&
32523256
(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
@@ -3286,6 +3290,8 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
32863290
i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
32873291
if (!adev->ip_blocks[i].status.late_initialized)
32883292
continue;
3293+
if (!adev->ip_blocks[i].version)
3294+
continue;
32893295
/* skip PG for GFX, SDMA on S0ix */
32903296
if (adev->in_s0ix &&
32913297
(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
@@ -3493,6 +3499,8 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
34933499
int i, r;
34943500

34953501
for (i = 0; i < adev->num_ip_blocks; i++) {
3502+
if (!adev->ip_blocks[i].version)
3503+
continue;
34963504
if (!adev->ip_blocks[i].version->funcs->early_fini)
34973505
continue;
34983506

@@ -3570,6 +3578,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
35703578
if (!adev->ip_blocks[i].status.sw)
35713579
continue;
35723580

3581+
if (!adev->ip_blocks[i].version)
3582+
continue;
35733583
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
35743584
amdgpu_ucode_free_bo(adev);
35753585
amdgpu_free_static_csa(&adev->virt.csa_obj);
@@ -3596,6 +3606,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
35963606
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
35973607
if (!adev->ip_blocks[i].status.late_initialized)
35983608
continue;
3609+
if (!adev->ip_blocks[i].version)
3610+
continue;
35993611
if (adev->ip_blocks[i].version->funcs->late_fini)
36003612
adev->ip_blocks[i].version->funcs->late_fini(&adev->ip_blocks[i]);
36013613
adev->ip_blocks[i].status.late_initialized = false;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev)
8383
{
8484
struct amdgpu_device *adev = drm_to_adev(dev);
8585

86-
if (adev == NULL)
86+
if (adev == NULL || !adev->num_ip_blocks)
8787
return;
8888

8989
amdgpu_unregister_gpu_instance(adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -368,15 +368,15 @@ struct amdgpu_mode_info {
368368

369369
struct drm_property *plane_ctm_property;
370370
/**
371-
* @shaper_lut_property: Plane property to set pre-blending shaper LUT
372-
* that converts color content before 3D LUT. If
373-
* plane_shaper_tf_property != Identity TF, AMD color module will
371+
* @plane_shaper_lut_property: Plane property to set pre-blending
372+
* shaper LUT that converts color content before 3D LUT.
373+
* If plane_shaper_tf_property != Identity TF, AMD color module will
374374
* combine the user LUT values with pre-defined TF into the LUT
375375
* parameters to be programmed.
376376
*/
377377
struct drm_property *plane_shaper_lut_property;
378378
/**
379-
* @shaper_lut_size_property: Plane property for the size of
379+
* @plane_shaper_lut_size_property: Plane property for the size of
380380
* pre-blending shaper LUT as supported by the driver (read-only).
381381
*/
382382
struct drm_property *plane_shaper_lut_size_property;
@@ -400,10 +400,10 @@ struct amdgpu_mode_info {
400400
*/
401401
struct drm_property *plane_lut3d_property;
402402
/**
403-
* @plane_degamma_lut_size_property: Plane property to define the max
404-
* size of 3D LUT as supported by the driver (read-only). The max size
405-
* is the max size of one dimension and, therefore, the max number of
406-
* entries for 3D LUT array is the 3D LUT size cubed;
403+
* @plane_lut3d_size_property: Plane property to define the max size
404+
* of 3D LUT as supported by the driver (read-only). The max size is
405+
* the max size of one dimension and, therefore, the max number of
406+
* entries for 3D LUT array is the 3D LUT size cubed.
407407
*/
408408
struct drm_property *plane_lut3d_size_property;
409409
/**

‎drivers/gpu/drm/amd/amdgpu/mes_v12_0.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -731,6 +731,9 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
731731
int i;
732732
struct amdgpu_device *adev = mes->adev;
733733
union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
734+
uint32_t mes_rev = (pipe == AMDGPU_MES_SCHED_PIPE) ?
735+
(mes->sched_version & AMDGPU_MES_VERSION_MASK) :
736+
(mes->kiq_version & AMDGPU_MES_VERSION_MASK);
734737

735738
memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
736739

@@ -785,7 +788,7 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
785788
* handling support, other queue will not use the oversubscribe timer.
786789
* handling mode - 0: disabled; 1: basic version; 2: basic+ version
787790
*/
788-
mes_set_hw_res_pkt.oversubscription_timer = 50;
791+
mes_set_hw_res_pkt.oversubscription_timer = mes_rev < 0x8b ? 0 : 50;
789792
mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;
790793

791794
if (amdgpu_mes_log_enable) {

‎drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -593,6 +593,7 @@ int pqm_update_queue_properties(struct process_queue_manager *pqm,
593593
p->queue_size)) {
594594
pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n",
595595
p->queue_address, p->queue_size);
596+
amdgpu_bo_unreserve(vm->root.bo);
596597
return -EFAULT;
597598
}
598599

‎drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,11 @@
3838
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
3939
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
4040
SR(DISPCLK_FREQ_CHANGE_CNTL),\
41-
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
41+
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\
42+
SR(MICROSECOND_TIME_BASE_DIV),\
43+
SR(MILLISECOND_TIME_BASE_DIV),\
44+
SR(DCCG_GATE_DISABLE_CNTL),\
45+
SR(DCCG_GATE_DISABLE_CNTL2)
4246

4347
#define DCCG_REG_LIST_DCN2() \
4448
DCCG_COMMON_REG_LIST_DCN_BASE(),\

‎drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c‎

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -96,14 +96,33 @@ static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppcl
9696
dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
9797
}
9898

99+
/*
100+
* On DCN21 S0i3 resume, BIOS programs MICROSECOND_TIME_BASE_DIV to
101+
* 0x00120464 as a marker that golden init has already been done.
102+
* dcn21_s0i3_golden_init_wa() reads this marker later in bios_golden_init()
103+
* to decide whether to skip golden init.
104+
*
105+
* dccg2_init() unconditionally overwrites MICROSECOND_TIME_BASE_DIV to
106+
* 0x00120264, destroying the marker before it can be read.
107+
*
108+
* Guard the call: if the S0i3 marker is present, skip dccg2_init() so the
109+
* WA can function correctly. bios_golden_init() will handle init in that case.
110+
*/
111+
static void dccg21_init(struct dccg *dccg)
112+
{
113+
if (dccg2_is_s0i3_golden_init_wa_done(dccg))
114+
return;
115+
116+
dccg2_init(dccg);
117+
}
99118

100119
static const struct dccg_funcs dccg21_funcs = {
101120
.update_dpp_dto = dccg21_update_dpp_dto,
102121
.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
103122
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
104123
.otg_add_pixel = dccg2_otg_add_pixel,
105124
.otg_drop_pixel = dccg2_otg_drop_pixel,
106-
.dccg_init = dccg2_init,
125+
.dccg_init = dccg21_init,
107126
.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
108127
.allow_clock_gating = dccg2_allow_clock_gating,
109128
.enable_memory_low_power = dccg2_enable_memory_low_power,

‎drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,13 @@
3434
DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
3535
DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
3636
DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
37-
SR(REFCLK_CNTL)
37+
SR(REFCLK_CNTL),\
38+
SR(DISPCLK_FREQ_CHANGE_CNTL),\
39+
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\
40+
SR(MICROSECOND_TIME_BASE_DIV),\
41+
SR(MILLISECOND_TIME_BASE_DIV),\
42+
SR(DCCG_GATE_DISABLE_CNTL),\
43+
SR(DCCG_GATE_DISABLE_CNTL2)
3844

3945
#define DCCG_MASK_SH_LIST_DCN301(mask_sh) \
4046
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\

‎drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,9 +64,12 @@
6464
SR(DSCCLK1_DTO_PARAM),\
6565
SR(DSCCLK2_DTO_PARAM),\
6666
SR(DSCCLK_DTO_CTRL),\
67+
SR(DCCG_GATE_DISABLE_CNTL),\
6768
SR(DCCG_GATE_DISABLE_CNTL2),\
6869
SR(DCCG_GATE_DISABLE_CNTL3),\
69-
SR(HDMISTREAMCLK0_DTO_PARAM)
70+
SR(HDMISTREAMCLK0_DTO_PARAM),\
71+
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\
72+
SR(MICROSECOND_TIME_BASE_DIV)
7073

7174

7275
#define DCCG_MASK_SH_LIST_DCN31(mask_sh) \

‎drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,11 +70,14 @@
7070
SR(DSCCLK2_DTO_PARAM),\
7171
SR(DSCCLK3_DTO_PARAM),\
7272
SR(DSCCLK_DTO_CTRL),\
73+
SR(DCCG_GATE_DISABLE_CNTL),\
7374
SR(DCCG_GATE_DISABLE_CNTL2),\
7475
SR(DCCG_GATE_DISABLE_CNTL3),\
7576
SR(HDMISTREAMCLK0_DTO_PARAM),\
7677
SR(OTG_PIXEL_RATE_DIV),\
77-
SR(DTBCLK_P_CNTL)
78+
SR(DTBCLK_P_CNTL),\
79+
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\
80+
SR(MICROSECOND_TIME_BASE_DIV)
7881

7982
#define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \
8083
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\

0 commit comments

Comments
 (0)