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Yang Wangalexdeucher
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drm/amd/pm: fix issue of missing '*' on pp_dpm_xxx nodes
refine the code to fix '*' missing on pp_dpm_xxx series node. e.g.: missing '*' on navi10 pp_dpm_sclk $ cat /sys/class/drm/card0/device/pp_dpm_sclk 0: 300Mhz 1: 1930Mhz (missing symbol '*') Fixes: a08ea4b ("drm/amd/pm: Add a helper to show dpm table") Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Lines changed: 16 additions & 15 deletions

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drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1286,11 +1286,11 @@ int smu_cmn_print_dpm_clk_levels(struct smu_context *smu,
12861286
struct smu_dpm_table *dpm_table,
12871287
uint32_t cur_clk, char *buf, int *offset)
12881288
{
1289-
uint32_t min_clk, level_index, count;
1290-
uint32_t freq_values[3] = { 0 };
1289+
uint32_t min_clk, max_clk, level_index, count;
1290+
uint32_t freq_values[3];
1291+
int size, lvl, i;
12911292
bool is_fine_grained;
12921293
bool is_deep_sleep;
1293-
int size, lvl, i;
12941294
bool freq_match;
12951295

12961296
if (!dpm_table || !buf)
@@ -1301,6 +1301,7 @@ int smu_cmn_print_dpm_clk_levels(struct smu_context *smu,
13011301
count = dpm_table->count;
13021302
is_fine_grained = dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED;
13031303
min_clk = SMU_DPM_TABLE_MIN(dpm_table);
1304+
max_clk = SMU_DPM_TABLE_MAX(dpm_table);
13041305

13051306
/* Deep sleep - current clock < min_clock/2, TBD: cur_clk = 0 as GFXOFF */
13061307
is_deep_sleep = cur_clk < min_clk / 2;
@@ -1321,22 +1322,22 @@ int smu_cmn_print_dpm_clk_levels(struct smu_context *smu,
13211322
freq_match ? "*" : "");
13221323
}
13231324
} else {
1325+
count = 2;
13241326
freq_values[0] = min_clk;
1325-
freq_values[2] = SMU_DPM_TABLE_MAX(dpm_table);
1326-
freq_values[1] = cur_clk;
1327+
freq_values[1] = max_clk;
13271328

1328-
lvl = -1;
13291329
if (!is_deep_sleep) {
1330-
lvl = 1;
1331-
if (smu_cmn_freqs_match(cur_clk, freq_values[0]))
1330+
if (smu_cmn_freqs_match(cur_clk, min_clk)) {
13321331
lvl = 0;
1333-
else if (smu_cmn_freqs_match(cur_clk, freq_values[2]))
1334-
lvl = 2;
1335-
}
1336-
count = 3;
1337-
if (lvl != 1) {
1338-
count = 2;
1339-
freq_values[1] = freq_values[2];
1332+
} else if (smu_cmn_freqs_match(cur_clk, max_clk)) {
1333+
lvl = 1;
1334+
} else {
1335+
/* NOTE: use index '1' to show current clock value */
1336+
lvl = 1;
1337+
count = 3;
1338+
freq_values[1] = cur_clk;
1339+
freq_values[2] = max_clk;
1340+
}
13401341
}
13411342

13421343
for (i = 0; i < count; i++) {

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