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andredkrzk
andred
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clk: samsung: gs101: harmonise symbol names (clock arrays)
Most symbols for the clock descriptions (arrays) don't have a cmu_ prefix and all symbols have a _clks suffix where appropriate. Update the few outliers to also fall into this same scheme for consistency. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20260205-clk-gs101-symbol-names-v1-1-a7d9a7a4d108@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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1 file changed

Lines changed: 26 additions & 26 deletions

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‎drivers/clk/samsung/clk-gs101.c‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -339,7 +339,7 @@
339339
#define GENERALIO_ACD_CHANNEL_3 0x3f0c
340340
#define GENERALIO_ACD_MASK 0x3f14
341341

342-
static const unsigned long cmu_top_clk_regs[] __initconst = {
342+
static const unsigned long top_clk_regs[] __initconst = {
343343
PLL_LOCKTIME_PLL_SHARED0,
344344
PLL_LOCKTIME_PLL_SHARED1,
345345
PLL_LOCKTIME_PLL_SHARED2,
@@ -638,7 +638,7 @@ static const unsigned long cmu_top_clk_regs[] __initconst = {
638638
GENERALIO_ACD_MASK,
639639
};
640640

641-
static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
641+
static const struct samsung_pll_clock top_pll_clks[] __initconst = {
642642
/* CMU_TOP_PURECLKCOMP */
643643
PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
644644
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
@@ -952,7 +952,7 @@ PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1",
952952
* For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC
953953
*/
954954

955-
static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
955+
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
956956
MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
957957
PLL_CON0_PLL_SHARED0, 4, 1),
958958
MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
@@ -1108,7 +1108,7 @@ static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
11081108
CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
11091109
};
11101110

1111-
static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
1111+
static const struct samsung_div_clock top_div_clks[] __initconst = {
11121112
DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
11131113
CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
11141114
DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
@@ -1253,13 +1253,13 @@ static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
12531253
"mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
12541254
};
12551255

1256-
static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
1256+
static const struct samsung_fixed_factor_clock top_ffactor_clks[] __initconst = {
12571257
FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg",
12581258
"gout_cmu_hsi0_usbdpdbg", 1, 4, 0),
12591259
FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
12601260
};
12611261

1262-
static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
1262+
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
12631263
GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",
12641264
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),
12651265
GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",
@@ -1425,19 +1425,19 @@ static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
14251425
};
14261426

14271427
static const struct samsung_cmu_info top_cmu_info __initconst = {
1428-
.pll_clks = cmu_top_pll_clks,
1429-
.nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks),
1430-
.mux_clks = cmu_top_mux_clks,
1431-
.nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks),
1432-
.div_clks = cmu_top_div_clks,
1433-
.nr_div_clks = ARRAY_SIZE(cmu_top_div_clks),
1434-
.fixed_factor_clks = cmu_top_ffactor,
1435-
.nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor),
1436-
.gate_clks = cmu_top_gate_clks,
1437-
.nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks),
1428+
.pll_clks = top_pll_clks,
1429+
.nr_pll_clks = ARRAY_SIZE(top_pll_clks),
1430+
.mux_clks = top_mux_clks,
1431+
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
1432+
.div_clks = top_div_clks,
1433+
.nr_div_clks = ARRAY_SIZE(top_div_clks),
1434+
.fixed_factor_clks = top_ffactor_clks,
1435+
.nr_fixed_factor_clks = ARRAY_SIZE(top_ffactor_clks),
1436+
.gate_clks = top_gate_clks,
1437+
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
14381438
.nr_clk_ids = CLKS_NR_TOP,
1439-
.clk_regs = cmu_top_clk_regs,
1440-
.nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs),
1439+
.clk_regs = top_clk_regs,
1440+
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
14411441
.auto_clock_gate = true,
14421442
.gate_dbg_offset = GS101_GATE_DBG_OFFSET,
14431443
.option_offset = CMU_CMU_TOP_CONTROLLER_OPTION,
@@ -2434,15 +2434,15 @@ PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll",
24342434
"dout_hsi0_usb31drd",
24352435
"fout_usb_pll" };
24362436

2437-
static const struct samsung_pll_rate_table cmu_hsi0_usb_pll_rates[] __initconst = {
2437+
static const struct samsung_pll_rate_table hsi0_usb_pll_rates[] __initconst = {
24382438
PLL_35XX_RATE(24576000, 19200000, 150, 6, 5),
24392439
{ /* sentinel */ }
24402440
};
24412441

2442-
static const struct samsung_pll_clock cmu_hsi0_pll_clks[] __initconst = {
2442+
static const struct samsung_pll_clock hsi0_pll_clks[] __initconst = {
24432443
PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
24442444
PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB,
2445-
cmu_hsi0_usb_pll_rates),
2445+
hsi0_usb_pll_rates),
24462446
};
24472447

24482448
static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
@@ -2660,8 +2660,8 @@ static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = {
26602660
};
26612661

26622662
static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
2663-
.pll_clks = cmu_hsi0_pll_clks,
2664-
.nr_pll_clks = ARRAY_SIZE(cmu_hsi0_pll_clks),
2663+
.pll_clks = hsi0_pll_clks,
2664+
.nr_pll_clks = ARRAY_SIZE(hsi0_pll_clks),
26652665
.mux_clks = hsi0_mux_clks,
26662666
.nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
26672667
.div_clks = hsi0_div_clks,
@@ -2791,7 +2791,7 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
27912791
#define QCH_CON_UFS_EMBD_QCH_FMP 0x3094
27922792
#define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00
27932793

2794-
static const unsigned long cmu_hsi2_clk_regs[] __initconst = {
2794+
static const unsigned long hsi2_clk_regs[] __initconst = {
27952795
PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER,
27962796
PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER,
27972797
PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
@@ -3166,8 +3166,8 @@ static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
31663166
.gate_clks = hsi2_gate_clks,
31673167
.nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks),
31683168
.nr_clk_ids = CLKS_NR_HSI2,
3169-
.clk_regs = cmu_hsi2_clk_regs,
3170-
.nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs),
3169+
.clk_regs = hsi2_clk_regs,
3170+
.nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs),
31713171
.sysreg_clk_regs = dcrg_memclk_sysreg,
31723172
.nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
31733173
.clk_name = "bus",

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