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Yuanjie Yanglumag
Yuanjie Yang
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lumag
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drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0
DPU version 13.0.0 introduces structural changes including register additions, removals, and relocations. Refactor SSPP-related code to be compatible with DPU 13.0.0 modifications. Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/698710/ Link: https://lore.kernel.org/r/20260115092749.533-10-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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2 files changed

Lines changed: 111 additions & 41 deletions

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‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c‎

Lines changed: 59 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -147,11 +147,18 @@
147147
static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
148148
{
149149
struct dpu_hw_sspp *ctx = pipe->sspp;
150-
u32 mode_mask;
151150

152151
if (!ctx)
153152
return;
154153

154+
dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE);
155+
}
156+
157+
void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
158+
struct dpu_hw_sspp *ctx, u32 op_mode_off)
159+
{
160+
u32 mode_mask;
161+
155162
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
156163
/**
157164
* if rect index is RECT_SOLO, we cannot expect a
@@ -160,18 +167,18 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
160167
*/
161168
mode_mask = 0;
162169
} else {
163-
mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE);
170+
mode_mask = DPU_REG_READ(&ctx->hw, op_mode_off);
164171
mode_mask |= pipe->multirect_index;
165172
if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
166173
mode_mask |= BIT(2);
167174
else
168175
mode_mask &= ~BIT(2);
169176
}
170177

171-
DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask);
178+
DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask);
172179
}
173180

174-
static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
181+
void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
175182
u32 mask, u8 en)
176183
{
177184
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
@@ -191,7 +198,7 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
191198
DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);
192199
}
193200

194-
static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
201+
void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
195202
u32 mask, u8 en)
196203
{
197204
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
@@ -213,10 +220,6 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
213220
const struct msm_format *fmt, u32 flags)
214221
{
215222
struct dpu_hw_sspp *ctx = pipe->sspp;
216-
struct dpu_hw_blk_reg_map *c;
217-
u32 chroma_samp, unpack, src_format;
218-
u32 opmode = 0;
219-
u32 fast_clear = 0;
220223
u32 op_mode_off, unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_error_off;
221224

222225
if (!ctx || !fmt)
@@ -244,6 +247,21 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
244247
}
245248
}
246249

250+
dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
251+
unpack_pat_off, format_off,
252+
ubwc_ctrl_off, ubwc_error_off);
253+
}
254+
255+
void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
256+
u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off,
257+
u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off,
258+
u32 ubwc_error_off)
259+
{
260+
struct dpu_hw_blk_reg_map *c;
261+
u32 chroma_samp, unpack, src_format;
262+
u32 opmode;
263+
u32 fast_clear;
264+
247265
c = &ctx->hw;
248266
opmode = DPU_REG_READ(c, op_mode_off);
249267
opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
@@ -331,10 +349,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
331349

332350
/* update scaler opmode, if appropriate */
333351
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
334-
_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
352+
dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
335353
MSM_FORMAT_IS_YUV(fmt));
336354
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
337-
_sspp_setup_csc10_opmode(ctx,
355+
dpu_hw_sspp_setup_csc10_opmode(ctx,
338356
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
339357
MSM_FORMAT_IS_YUV(fmt));
340358

@@ -403,7 +421,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
403421
tot_req_pixels[3]);
404422
}
405423

406-
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
424+
void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
407425
struct dpu_hw_scaler3_cfg *scaler3_cfg,
408426
const struct msm_format *format)
409427
{
@@ -423,15 +441,11 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
423441
struct dpu_sw_pipe_cfg *cfg)
424442
{
425443
struct dpu_hw_sspp *ctx = pipe->sspp;
426-
struct dpu_hw_blk_reg_map *c;
427-
u32 src_size, src_xy, dst_size, dst_xy;
428444
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
429445

430446
if (!ctx || !cfg)
431447
return;
432448

433-
c = &ctx->hw;
434-
435449
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
436450
pipe->multirect_index == DPU_SSPP_RECT_0) {
437451
src_size_off = SSPP_SRC_SIZE;
@@ -445,20 +459,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
445459
out_xy_off = SSPP_OUT_XY_REC1;
446460
}
447461

448-
449-
/* src and dest rect programming */
450-
src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
451-
src_size = (drm_rect_height(&cfg->src_rect) << 16) |
452-
drm_rect_width(&cfg->src_rect);
453-
dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
454-
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
455-
drm_rect_width(&cfg->dst_rect);
456-
457-
/* rectangle register programming */
458-
DPU_REG_WRITE(c, src_size_off, src_size);
459-
DPU_REG_WRITE(c, src_xy_off, src_xy);
460-
DPU_REG_WRITE(c, out_size_off, dst_size);
461-
DPU_REG_WRITE(c, out_xy_off, dst_xy);
462+
dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
463+
src_xy_off, out_size_off, out_xy_off);
462464
}
463465

464466
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
@@ -515,7 +517,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
515517
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);
516518
}
517519

518-
static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
520+
void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
519521
const struct dpu_csc_cfg *data)
520522
{
521523
u32 offset;
@@ -537,21 +539,31 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
537539
static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
538540
{
539541
struct dpu_hw_sspp *ctx = pipe->sspp;
540-
struct dpu_hw_fmt_layout cfg;
542+
u32 const_clr_off;
541543

542544
if (!ctx)
543545
return;
544546

547+
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
548+
pipe->multirect_index == DPU_SSPP_RECT_0)
549+
const_clr_off = SSPP_SRC_CONSTANT_COLOR;
550+
else
551+
const_clr_off = SSPP_SRC_CONSTANT_COLOR_REC1;
552+
553+
dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
554+
}
555+
556+
void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
557+
u32 color, struct dpu_hw_sspp *ctx,
558+
u32 const_clr_off)
559+
{
560+
struct dpu_hw_fmt_layout cfg;
561+
545562
/* cleanup source addresses */
546563
memset(&cfg, 0, sizeof(cfg));
547564
ctx->ops.setup_sourceaddress(pipe, &cfg);
548565

549-
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
550-
pipe->multirect_index == DPU_SSPP_RECT_0)
551-
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color);
552-
else
553-
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1,
554-
color);
566+
DPU_REG_WRITE(&ctx->hw, const_clr_off, color);
555567
}
556568

557569
static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
@@ -565,14 +577,20 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
565577
cfg);
566578
}
567579

580+
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
581+
bool danger_safe_en, u32 ctrl_off)
582+
{
583+
DPU_REG_WRITE(&ctx->hw, ctrl_off,
584+
danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
585+
}
586+
568587
static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
569588
bool danger_safe_en)
570589
{
571590
if (!ctx)
572591
return;
573592

574-
DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
575-
danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
593+
dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL);
576594
}
577595

578596
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
@@ -627,7 +645,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c,
627645
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
628646

629647
if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
630-
c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
648+
c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
631649

632650
if (test_bit(DPU_SSPP_CDP, &features))
633651
c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -332,5 +332,57 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
332332
int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
333333
struct dentry *entry);
334334

335+
void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
336+
u32 mask, u8 en);
337+
338+
void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
339+
u32 mask, u8 en);
340+
341+
void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
342+
struct dpu_hw_scaler3_cfg *scaler3_cfg,
343+
const struct msm_format *format);
344+
345+
void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
346+
const struct dpu_csc_cfg *data);
347+
348+
void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
349+
struct dpu_hw_sspp *ctx,
350+
u32 op_mode_off);
351+
352+
void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
353+
u32 flags, struct dpu_hw_sspp *ctx,
354+
u32 op_mode_off, u32 unpack_pat_off, u32 format_off,
355+
u32 ubwc_ctrl_off, u32 ubwc_err_off);
356+
357+
static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *cfg,
358+
struct dpu_hw_sspp *ctx, u32 src_size_off,
359+
u32 src_xy_off, u32 out_size_off, u32 out_xy_off)
360+
{
361+
struct dpu_hw_blk_reg_map *c;
362+
u32 src_size, src_xy, dst_size, dst_xy;
363+
364+
c = &ctx->hw;
365+
366+
/* src and dest rect programming */
367+
src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
368+
src_size = (drm_rect_height(&cfg->src_rect) << 16) |
369+
drm_rect_width(&cfg->src_rect);
370+
dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
371+
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
372+
drm_rect_width(&cfg->dst_rect);
373+
374+
/* rectangle register programming */
375+
DPU_REG_WRITE(c, src_size_off, src_size);
376+
DPU_REG_WRITE(c, src_xy_off, src_xy);
377+
DPU_REG_WRITE(c, out_size_off, dst_size);
378+
DPU_REG_WRITE(c, out_xy_off, dst_xy);
379+
}
380+
381+
void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
382+
u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off);
383+
384+
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
385+
bool danger_safe_en, u32 ctrl_off);
386+
335387
#endif /*_DPU_HW_SSPP_H */
336388

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