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rrama-nexthopgregkh
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serial: 8250_fintek: Add support for F81214E
The F81214E is a LPC/eSPI to 2 UART Super I/O chip. Functionally, it is the same as the F81216E. The only difference is that the F81216E has 4 UART ports, whereas the F81214E has 2 UART ports. Signed-off-by: Ravi Rama <ravi.rama@nexthop.ai> Link: https://patch.msgid.link/20260313194731.2671-1-ravi.rama@nexthop.ai Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Lines changed: 9 additions & 1 deletion

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drivers/tty/serial/8250/8250_fintek.c

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0
22
/*
3-
* Probe for F81216A LPC to 4 UART
3+
* Probe for F81216A LPC to 4 UART and F81214E LPC/eSPI to 2 UART
44
*
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* Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
66
*/
@@ -23,6 +23,7 @@
2323
#define CHIP_ID_F81216AD 0x1602
2424
#define CHIP_ID_F81216E 0x1617
2525
#define CHIP_ID_F81216H 0x0501
26+
#define CHIP_ID_F81214E 0x1417
2627
#define CHIP_ID_F81216 0x0802
2728
#define VENDOR_ID1 0x23
2829
#define VENDOR_ID1_VAL 0x19
@@ -161,6 +162,7 @@ static int fintek_8250_check_id(struct fintek_8250 *pdata)
161162
case CHIP_ID_F81216AD:
162163
case CHIP_ID_F81216E:
163164
case CHIP_ID_F81216H:
165+
case CHIP_ID_F81214E:
164166
case CHIP_ID_F81216:
165167
break;
166168
default:
@@ -185,6 +187,7 @@ static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
185187
case CHIP_ID_F81216AD:
186188
case CHIP_ID_F81216E:
187189
case CHIP_ID_F81216H:
190+
case CHIP_ID_F81214E:
188191
case CHIP_ID_F81216:
189192
*min = F81216_LDN_LOW;
190193
*max = F81216_LDN_HIGH;
@@ -255,6 +258,7 @@ static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
255258
case CHIP_ID_F81216AD:
256259
case CHIP_ID_F81216E:
257260
case CHIP_ID_F81216H:
261+
case CHIP_ID_F81214E:
258262
case CHIP_ID_F81216:
259263
sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE,
260264
IRQ_SHARE);
@@ -269,6 +273,7 @@ static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
269273
switch (pdata->pid) {
270274
case CHIP_ID_F81216E: /* 128Bytes FIFO */
271275
case CHIP_ID_F81216H:
276+
case CHIP_ID_F81214E:
272277
case CHIP_ID_F81966:
273278
case CHIP_ID_F81866:
274279
sio_write_mask_reg(pdata, FIFO_CTRL,
@@ -304,6 +309,7 @@ static void fintek_8250_set_termios(struct uart_port *port,
304309
switch (pdata->pid) {
305310
case CHIP_ID_F81216E:
306311
case CHIP_ID_F81216H:
312+
case CHIP_ID_F81214E:
307313
reg = RS485;
308314
break;
309315
case CHIP_ID_F81966:
@@ -354,6 +360,7 @@ static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
354360
switch (pdata->pid) {
355361
case CHIP_ID_F81216E:
356362
case CHIP_ID_F81216H:
363+
case CHIP_ID_F81214E:
357364
case CHIP_ID_F81966:
358365
case CHIP_ID_F81866:
359366
uart->port.set_termios = fintek_8250_set_termios;
@@ -446,6 +453,7 @@ static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
446453
break;
447454

448455
case CHIP_ID_F81216E: /* F81216E does not support RS485 delays */
456+
case CHIP_ID_F81214E: /* F81214E does not support RS485 delays */
449457
uart->port.rs485_config = fintek_8250_rs485_config;
450458
uart->port.rs485_supported = fintek_8250_rs485_supported;
451459
break;

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