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amd-pvishwakalexdeucher
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drm/amd: Enable SMU 15_0_0 support
Add SMU 15_0_0 v2: rebase (Alex) v3: fix clang build (Alex) Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent a68654b commit c7fc0f3

12 files changed

Lines changed: 3526 additions & 2 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2238,6 +2238,9 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
22382238
case IP_VERSION(14, 0, 5):
22392239
amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
22402240
break;
2241+
case IP_VERSION(15, 0, 0):
2242+
amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block);
2243+
break;
22412244
default:
22422245
dev_err(adev->dev,
22432246
"Failed to add smu ip block(MP1_HWIP:0x%x)\n",

‎drivers/gpu/drm/amd/include/kgd_pp_interface.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
2929
extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
3030
extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
3131
extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
32+
extern const struct amdgpu_ip_block_version smu_v15_0_ip_block;
3233

3334
enum smu_temp_metric_type {
3435
SMU_TEMP_METRIC_BASEBOARD,

‎drivers/gpu/drm/amd/pm/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ subdir-ccflags-y += \
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-I$(FULL_AMD_PATH)/pm/swsmu/smu12 \
3232
-I$(FULL_AMD_PATH)/pm/swsmu/smu13 \
3333
-I$(FULL_AMD_PATH)/pm/swsmu/smu14 \
34+
-I$(FULL_AMD_PATH)/pm/swsmu/smu15 \
3435
-I$(FULL_AMD_PATH)/pm/powerplay/inc \
3536
-I$(FULL_AMD_PATH)/pm/powerplay/smumgr\
3637
-I$(FULL_AMD_PATH)/pm/powerplay/hwmgr \

‎drivers/gpu/drm/amd/pm/swsmu/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222

2323
AMD_SWSMU_PATH = ../pm/swsmu
2424

25-
SWSMU_LIBS = smu11 smu12 smu13 smu14
25+
SWSMU_LIBS = smu11 smu12 smu13 smu14 smu15
2626

2727
AMD_SWSMU = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/pm/swsmu/,$(SWSMU_LIBS)))
2828

‎drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@
4646
#include "smu_v13_0_7_ppt.h"
4747
#include "smu_v14_0_0_ppt.h"
4848
#include "smu_v14_0_2_ppt.h"
49+
#include "smu_v15_0_0_ppt.h"
4950
#include "amd_pcie.h"
5051

5152
/*
@@ -796,6 +797,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
796797
case IP_VERSION(14, 0, 3):
797798
smu_v14_0_2_set_ppt_funcs(smu);
798799
break;
800+
case IP_VERSION(15, 0, 0):
801+
smu_v15_0_0_set_ppt_funcs(smu);
802+
break;
799803
default:
800804
return -EINVAL;
801805
}
@@ -2806,6 +2810,14 @@ const struct amdgpu_ip_block_version smu_v14_0_ip_block = {
28062810
.funcs = &smu_ip_funcs,
28072811
};
28082812

2813+
const struct amdgpu_ip_block_version smu_v15_0_ip_block = {
2814+
.type = AMD_IP_BLOCK_TYPE_SMC,
2815+
.major = 15,
2816+
.minor = 0,
2817+
.rev = 0,
2818+
.funcs = &smu_ip_funcs,
2819+
};
2820+
28092821
const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle)
28102822
{
28112823
struct smu_context *smu = (struct smu_context *)handle;

‎drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1632,6 +1632,7 @@ typedef enum {
16321632
METRICS_THROTTLER_RESIDENCY_THM_CORE,
16331633
METRICS_THROTTLER_RESIDENCY_THM_GFX,
16341634
METRICS_THROTTLER_RESIDENCY_THM_SOC,
1635+
METRICS_AVERAGE_NPUCLK,
16351636
} MetricsMember_t;
16361637

16371638
enum smu_cmn2asic_mapping_type {

‎drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -288,7 +288,11 @@
288288
__SMU_DUMMY_MAP(GetBadPageIpid), \
289289
__SMU_DUMMY_MAP(EraseRasTable), \
290290
__SMU_DUMMY_MAP(SetFastPptLimit), \
291-
__SMU_DUMMY_MAP(GetFastPptLimit),
291+
__SMU_DUMMY_MAP(GetFastPptLimit), \
292+
__SMU_DUMMY_MAP(AllowZstates), \
293+
__SMU_DUMMY_MAP(GetSmartShiftStatus), \
294+
__SMU_DUMMY_MAP(EnableLSdma), \
295+
__SMU_DUMMY_MAP(DisableLSdma),
292296

293297
#undef __SMU_DUMMY_MAP
294298
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type

‎drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,247 @@
1+
/*
2+
* Copyright 2025 Advanced Micro Devices, Inc.
3+
*
4+
* Permission is hereby granted, free of charge, to any person obtaining a
5+
* copy of this software and associated documentation files (the "Software"),
6+
* to deal in the Software without restriction, including without limitation
7+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
* and/or sell copies of the Software, and to permit persons to whom the
9+
* Software is furnished to do so, subject to the following conditions:
10+
*
11+
* The above copyright notice and this permission notice shall be included in
12+
* all copies or substantial portions of the Software.
13+
*
14+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+
* OTHER DEALINGS IN THE SOFTWARE.
21+
*
22+
*/
23+
#ifndef __SMU_V15_0_H__
24+
#define __SMU_V15_0_H__
25+
26+
#include "amdgpu_smu.h"
27+
28+
#define SMU15_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29+
#define SMU15_DRIVER_IF_VERSION_SMU_V15_0 0x7
30+
31+
32+
#define FEATURE_MASK(feature) (1ULL << feature)
33+
34+
/* MP Apertures */
35+
#define MP0_Public 0x03800000
36+
#define MP0_SRAM 0x03900000
37+
#define MP1_Public 0x03b00000
38+
#define MP1_SRAM 0x03c00004
39+
40+
/* address block */
41+
#define smnMP1_FIRMWARE_FLAGS 0x3010024
42+
#define smnMP1_PUB_CTRL 0x3010d10
43+
44+
#define MAX_DPM_LEVELS 16
45+
#define MAX_PCIE_CONF 3
46+
47+
#define SMU15_TOOL_SIZE 0x19000
48+
49+
#define CTF_OFFSET_EDGE 5
50+
#define CTF_OFFSET_HOTSPOT 5
51+
#define CTF_OFFSET_MEM 5
52+
53+
extern const int decoded_link_speed[5];
54+
extern const int decoded_link_width[8];
55+
56+
#define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx])
57+
#define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx])
58+
59+
struct smu_15_0_max_sustainable_clocks {
60+
uint32_t display_clock;
61+
uint32_t phy_clock;
62+
uint32_t pixel_clock;
63+
uint32_t uclock;
64+
uint32_t dcef_clock;
65+
uint32_t soc_clock;
66+
};
67+
68+
struct smu_15_0_dpm_clk_level {
69+
bool enabled;
70+
uint32_t value;
71+
};
72+
73+
struct smu_15_0_dpm_table {
74+
uint32_t min; /* MHz */
75+
uint32_t max; /* MHz */
76+
uint32_t count;
77+
bool is_fine_grained;
78+
struct smu_15_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
79+
};
80+
81+
struct smu_15_0_pcie_table {
82+
uint8_t pcie_gen[MAX_PCIE_CONF];
83+
uint8_t pcie_lane[MAX_PCIE_CONF];
84+
uint16_t clk_freq[MAX_PCIE_CONF];
85+
uint32_t num_of_link_levels;
86+
};
87+
88+
struct smu_15_0_dpm_tables {
89+
struct smu_15_0_dpm_table soc_table;
90+
struct smu_15_0_dpm_table gfx_table;
91+
struct smu_15_0_dpm_table uclk_table;
92+
struct smu_15_0_dpm_table eclk_table;
93+
struct smu_15_0_dpm_table vclk_table;
94+
struct smu_15_0_dpm_table dclk_table;
95+
struct smu_15_0_dpm_table dcef_table;
96+
struct smu_15_0_dpm_table pixel_table;
97+
struct smu_15_0_dpm_table display_table;
98+
struct smu_15_0_dpm_table phy_table;
99+
struct smu_15_0_dpm_table fclk_table;
100+
struct smu_15_0_pcie_table pcie_table;
101+
};
102+
103+
struct smu_15_0_dpm_context {
104+
struct smu_15_0_dpm_tables dpm_tables;
105+
uint32_t workload_policy_mask;
106+
uint32_t dcef_min_ds_clk;
107+
};
108+
109+
enum smu_15_0_power_state {
110+
smu_15_0_POWER_STATE__D0 = 0,
111+
smu_15_0_POWER_STATE__D1,
112+
smu_15_0_POWER_STATE__D3, /* Sleep*/
113+
smu_15_0_POWER_STATE__D4, /* Hibernate*/
114+
smu_15_0_POWER_STATE__D5, /* Power off*/
115+
};
116+
117+
struct smu_15_0_power_context {
118+
uint32_t power_source;
119+
uint8_t in_power_limit_boost_mode;
120+
enum smu_15_0_power_state power_state;
121+
};
122+
123+
#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
124+
125+
int smu_v15_0_init_microcode(struct smu_context *smu);
126+
127+
void smu_v15_0_fini_microcode(struct smu_context *smu);
128+
129+
int smu_v15_0_load_microcode(struct smu_context *smu);
130+
131+
int smu_v15_0_init_smc_tables(struct smu_context *smu);
132+
133+
int smu_v15_0_fini_smc_tables(struct smu_context *smu);
134+
135+
int smu_v15_0_init_power(struct smu_context *smu);
136+
137+
int smu_v15_0_fini_power(struct smu_context *smu);
138+
139+
int smu_v15_0_check_fw_status(struct smu_context *smu);
140+
141+
int smu_v15_0_setup_pptable(struct smu_context *smu);
142+
143+
int smu_v15_0_get_vbios_bootup_values(struct smu_context *smu);
144+
145+
int smu_v15_0_check_fw_version(struct smu_context *smu);
146+
147+
int smu_v15_0_set_driver_table_location(struct smu_context *smu);
148+
149+
int smu_v15_0_set_tool_table_location(struct smu_context *smu);
150+
151+
int smu_v15_0_notify_memory_pool_location(struct smu_context *smu);
152+
153+
int smu_v15_0_system_features_control(struct smu_context *smu,
154+
bool en);
155+
156+
int smu_v15_0_set_allowed_mask(struct smu_context *smu);
157+
158+
int smu_v15_0_notify_display_change(struct smu_context *smu);
159+
160+
int smu_v15_0_get_current_power_limit(struct smu_context *smu,
161+
uint32_t *power_limit);
162+
163+
int smu_v15_0_set_power_limit(struct smu_context *smu,
164+
enum smu_ppt_limit_type limit_type,
165+
uint32_t limit);
166+
167+
int smu_v15_0_gfx_off_control(struct smu_context *smu, bool enable);
168+
169+
int smu_v15_0_register_irq_handler(struct smu_context *smu);
170+
171+
int smu_v15_0_baco_set_armd3_sequence(struct smu_context *smu,
172+
enum smu_baco_seq baco_seq);
173+
174+
int smu_v15_0_get_bamaco_support(struct smu_context *smu);
175+
176+
enum smu_baco_state smu_v15_0_baco_get_state(struct smu_context *smu);
177+
178+
int smu_v15_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
179+
180+
int smu_v15_0_baco_enter(struct smu_context *smu);
181+
int smu_v15_0_baco_exit(struct smu_context *smu);
182+
183+
int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
184+
uint32_t *min, uint32_t *max);
185+
186+
int smu_v15_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
187+
uint32_t min, uint32_t max, bool automatic);
188+
189+
int smu_v15_0_set_hard_freq_limited_range(struct smu_context *smu,
190+
enum smu_clk_type clk_type,
191+
uint32_t min,
192+
uint32_t max);
193+
194+
int smu_v15_0_set_performance_level(struct smu_context *smu,
195+
enum amd_dpm_forced_level level);
196+
197+
int smu_v15_0_set_power_source(struct smu_context *smu,
198+
enum smu_power_src_type power_src);
199+
200+
int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
201+
enum smu_clk_type clk_type,
202+
struct smu_15_0_dpm_table *single_dpm_table);
203+
204+
int smu_v15_0_gfx_ulv_control(struct smu_context *smu,
205+
bool enablement);
206+
207+
int smu_v15_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
208+
uint64_t event_arg);
209+
210+
int smu_v15_0_set_vcn_enable(struct smu_context *smu,
211+
bool enable,
212+
int inst);
213+
214+
int smu_v15_0_set_jpeg_enable(struct smu_context *smu,
215+
bool enable);
216+
217+
int smu_v15_0_init_pptable_microcode(struct smu_context *smu);
218+
219+
int smu_v15_0_run_btc(struct smu_context *smu);
220+
221+
int smu_v15_0_gpo_control(struct smu_context *smu,
222+
bool enablement);
223+
224+
int smu_v15_0_deep_sleep_control(struct smu_context *smu,
225+
bool enablement);
226+
227+
int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu);
228+
229+
int smu_v15_0_set_default_dpm_tables(struct smu_context *smu);
230+
231+
int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu,
232+
void **table,
233+
uint32_t *size,
234+
uint32_t pptable_id);
235+
236+
int smu_v15_0_od_edit_dpm_table(struct smu_context *smu,
237+
enum PP_OD_DPM_TABLE_COMMAND type,
238+
long input[], uint32_t size);
239+
240+
void smu_v15_0_set_smu_mailbox_registers(struct smu_context *smu);
241+
242+
int smu_v15_0_enable_thermal_alert(struct smu_context *smu);
243+
244+
int smu_v15_0_disable_thermal_alert(struct smu_context *smu);
245+
246+
#endif
247+
#endif

‎drivers/gpu/drm/amd/pm/swsmu/smu15/Makefile‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
#
2+
# Copyright 2025 Advanced Micro Devices, Inc.
3+
#
4+
# Permission is hereby granted, free of charge, to any person obtaining a
5+
# copy of this software and associated documentation files (the "Software"),
6+
# to deal in the Software without restriction, including without limitation
7+
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
# and/or sell copies of the Software, and to permit persons to whom the
9+
# Software is furnished to do so, subject to the following conditions:
10+
#
11+
# The above copyright notice and this permission notice shall be included in
12+
# all copies or substantial portions of the Software.
13+
#
14+
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+
# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+
# OTHER DEALINGS IN THE SOFTWARE.
21+
#
22+
#
23+
# Makefile for the 'smu manager' sub-component of powerplay.
24+
# It provides the smu management services for the driver.
25+
26+
SMU15_MGR = smu_v15_0.o smu_v15_0_0_ppt.o
27+
28+
AMD_SWSMU_SMU15MGR = $(addprefix $(AMD_SWSMU_PATH)/smu15/,$(SMU15_MGR))
29+
30+
AMD_POWERPLAY_FILES += $(AMD_SWSMU_SMU15MGR)

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