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wenmliuandersson
wenmliu
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arm64: dts: qcom: talos: Add camss node
Add node for the SM6150 camera subsystem. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260305-sm6150_evk-v6-2-38ce4360d5e0@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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‎arch/arm64/boot/dts/qcom/talos.dtsi‎

Lines changed: 200 additions & 0 deletions
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@@ -3955,6 +3955,206 @@
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#power-domain-cells = <1>;
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};
39573957

3958+
camss: isp@acb3000 {
3959+
compatible = "qcom,sm6150-camss";
3960+
3961+
reg = <0x0 0x0acb3000 0x0 0x1000>,
3962+
<0x0 0x0acba000 0x0 0x1000>,
3963+
<0x0 0x0acc8000 0x0 0x1000>,
3964+
<0x0 0x0ac65000 0x0 0x1000>,
3965+
<0x0 0x0ac66000 0x0 0x1000>,
3966+
<0x0 0x0ac67000 0x0 0x1000>,
3967+
<0x0 0x0acaf000 0x0 0x4000>,
3968+
<0x0 0x0acb6000 0x0 0x4000>,
3969+
<0x0 0x0acc4000 0x0 0x4000>,
3970+
<0x0 0x0ac6f000 0x0 0x3000>,
3971+
<0x0 0x0ac42000 0x0 0x5000>,
3972+
<0x0 0x0ac48000 0x0 0x1000>,
3973+
<0x0 0x0ac40000 0x0 0x1000>,
3974+
<0x0 0x0ac18000 0x0 0x3000>,
3975+
<0x0 0x0ac00000 0x0 0x6000>,
3976+
<0x0 0x0ac10000 0x0 0x8000>,
3977+
<0x0 0x0ac87000 0x0 0x3000>,
3978+
<0x0 0x0ac52000 0x0 0x4000>,
3979+
<0x0 0x0ac4e000 0x0 0x4000>,
3980+
<0x0 0x0ac6b000 0x0 0x0a00>;
3981+
reg-names = "csid0",
3982+
"csid1",
3983+
"csid_lite",
3984+
"csiphy0",
3985+
"csiphy1",
3986+
"csiphy2",
3987+
"vfe0",
3988+
"vfe1",
3989+
"vfe_lite",
3990+
"bps",
3991+
"camnoc",
3992+
"cpas_cdm",
3993+
"cpas_top",
3994+
"icp_csr",
3995+
"icp_qgic",
3996+
"icp_sierra",
3997+
"ipe0",
3998+
"jpeg_dma",
3999+
"jpeg_enc",
4000+
"lrme";
4001+
4002+
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4003+
<&gcc GCC_CAMERA_HF_AXI_CLK>,
4004+
<&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
4006+
<&camcc CAM_CC_CSIPHY0_CLK>,
4007+
<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY1_CLK>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4010+
<&camcc CAM_CC_CSIPHY2_CLK>,
4011+
<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4012+
<&camcc CAM_CC_SOC_AHB_CLK>,
4013+
<&camcc CAM_CC_IFE_0_CLK>,
4014+
<&camcc CAM_CC_IFE_0_AXI_CLK>,
4015+
<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4016+
<&camcc CAM_CC_IFE_0_CSID_CLK>,
4017+
<&camcc CAM_CC_IFE_1_CLK>,
4018+
<&camcc CAM_CC_IFE_1_AXI_CLK>,
4019+
<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4020+
<&camcc CAM_CC_IFE_1_CSID_CLK>,
4021+
<&camcc CAM_CC_IFE_LITE_CLK>,
4022+
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4023+
<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
4024+
<&camcc CAM_CC_BPS_CLK>,
4025+
<&camcc CAM_CC_BPS_AHB_CLK>,
4026+
<&camcc CAM_CC_BPS_AXI_CLK>,
4027+
<&camcc CAM_CC_BPS_AREG_CLK>,
4028+
<&camcc CAM_CC_ICP_CLK>,
4029+
<&camcc CAM_CC_IPE_0_CLK>,
4030+
<&camcc CAM_CC_IPE_0_AHB_CLK>,
4031+
<&camcc CAM_CC_IPE_0_AREG_CLK>,
4032+
<&camcc CAM_CC_IPE_0_AXI_CLK>,
4033+
<&camcc CAM_CC_JPEG_CLK>,
4034+
<&camcc CAM_CC_LRME_CLK>;
4035+
clock-names = "gcc_ahb",
4036+
"gcc_axi_hf",
4037+
"camnoc_axi",
4038+
"cpas_ahb",
4039+
"csiphy0",
4040+
"csiphy0_timer",
4041+
"csiphy1",
4042+
"csiphy1_timer",
4043+
"csiphy2",
4044+
"csiphy2_timer",
4045+
"soc_ahb",
4046+
"vfe0",
4047+
"vfe0_axi",
4048+
"vfe0_cphy_rx",
4049+
"vfe0_csid",
4050+
"vfe1",
4051+
"vfe1_axi",
4052+
"vfe1_cphy_rx",
4053+
"vfe1_csid",
4054+
"vfe_lite",
4055+
"vfe_lite_cphy_rx",
4056+
"vfe_lite_csid",
4057+
"bps",
4058+
"bps_ahb",
4059+
"bps_axi",
4060+
"bps_areg",
4061+
"icp",
4062+
"ipe0",
4063+
"ipe0_ahb",
4064+
"ipe0_areg",
4065+
"ipe0_axi",
4066+
"jpeg",
4067+
"lrme";
4068+
4069+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4070+
&config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
4071+
<&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS
4072+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4073+
<&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS
4074+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4075+
<&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
4076+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
4077+
interconnect-names = "ahb",
4078+
"hf_0",
4079+
"hf_1",
4080+
"sf_mnoc";
4081+
4082+
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING 0>,
4083+
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING 0>,
4084+
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING 0>,
4085+
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>,
4086+
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>,
4087+
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>,
4088+
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING 0>,
4089+
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING 0>,
4090+
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING 0>,
4091+
<GIC_SPI 459 IRQ_TYPE_EDGE_RISING 0>,
4092+
<GIC_SPI 461 IRQ_TYPE_EDGE_RISING 0>,
4093+
<GIC_SPI 463 IRQ_TYPE_EDGE_RISING 0>,
4094+
<GIC_SPI 475 IRQ_TYPE_EDGE_RISING 0>,
4095+
<GIC_SPI 474 IRQ_TYPE_EDGE_RISING 0>,
4096+
<GIC_SPI 476 IRQ_TYPE_EDGE_RISING 0>;
4097+
interrupt-names = "csid0",
4098+
"csid1",
4099+
"csid_lite",
4100+
"csiphy0",
4101+
"csiphy1",
4102+
"csiphy2",
4103+
"vfe0",
4104+
"vfe1",
4105+
"vfe_lite",
4106+
"camnoc",
4107+
"cdm",
4108+
"icp",
4109+
"jpeg_dma",
4110+
"jpeg_enc",
4111+
"lrme";
4112+
4113+
iommus = <&apps_smmu 0x0820 0x40>,
4114+
<&apps_smmu 0x0840 0x00>,
4115+
<&apps_smmu 0x0860 0x40>,
4116+
<&apps_smmu 0x0c00 0x00>,
4117+
<&apps_smmu 0x0cc0 0x00>,
4118+
<&apps_smmu 0x0c80 0x00>,
4119+
<&apps_smmu 0x0ca0 0x00>,
4120+
<&apps_smmu 0x0d00 0x00>,
4121+
<&apps_smmu 0x0d20 0x00>,
4122+
<&apps_smmu 0x0d40 0x00>,
4123+
<&apps_smmu 0x0d80 0x20>,
4124+
<&apps_smmu 0x0da0 0x20>,
4125+
<&apps_smmu 0x0de2 0x00>;
4126+
4127+
power-domains = <&camcc IFE_0_GDSC>,
4128+
<&camcc IFE_1_GDSC>,
4129+
<&camcc TITAN_TOP_GDSC>,
4130+
<&camcc BPS_GDSC>,
4131+
<&camcc IPE_0_GDSC>;
4132+
power-domain-names = "ife0",
4133+
"ife1",
4134+
"top",
4135+
"bps",
4136+
"ipe";
4137+
4138+
status = "disabled";
4139+
4140+
ports {
4141+
#address-cells = <1>;
4142+
#size-cells = <0>;
4143+
4144+
port@0 {
4145+
reg = <0>;
4146+
};
4147+
4148+
port@1 {
4149+
reg = <1>;
4150+
};
4151+
4152+
port@2 {
4153+
reg = <2>;
4154+
};
4155+
};
4156+
};
4157+
39584158
camcc: clock-controller@ad00000 {
39594159
compatible = "qcom,qcs615-camcc";
39604160
reg = <0 0x0ad00000 0 0x10000>;

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