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Ketan Patilkrzk
Ketan Patil
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krzk
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memory: tegra: Group error handling related registers
Group MC error related registers into a struct as they could have SoC specific values. Tegra264 has different register offsets than the existing devices and so in order to add support for Tegra264 we need to first make this change. Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
1 parent 2413283 commit b8a177f

11 files changed

Lines changed: 71 additions & 39 deletions

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‎drivers/memory/tegra/mc.c‎

Lines changed: 32 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <linux/clk.h>
@@ -56,6 +56,23 @@ static const struct of_device_id tegra_mc_of_match[] = {
5656
};
5757
MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
5858

59+
const struct tegra_mc_regs tegra20_mc_regs = {
60+
.cfg_channel_enable = 0xdf8,
61+
.err_status = 0x08,
62+
.err_add = 0x0c,
63+
.err_add_hi = 0x11fc,
64+
.err_vpr_status = 0x654,
65+
.err_vpr_add = 0x658,
66+
.err_sec_status = 0x67c,
67+
.err_sec_add = 0x680,
68+
.err_mts_status = 0x9b0,
69+
.err_mts_add = 0x9b4,
70+
.err_gen_co_status = 0xc00,
71+
.err_gen_co_add = 0xc04,
72+
.err_route_status = 0x9c0,
73+
.err_route_add = 0x9c4,
74+
};
75+
5976
static void tegra_mc_devm_action_put_device(void *data)
6077
{
6178
struct tegra_mc *mc = data;
@@ -591,37 +608,37 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
591608

592609
switch (intmask) {
593610
case MC_INT_DECERR_VPR:
594-
status_reg = MC_ERR_VPR_STATUS;
595-
addr_reg = MC_ERR_VPR_ADR;
611+
status_reg = mc->soc->regs->err_vpr_status;
612+
addr_reg = mc->soc->regs->err_vpr_add;
596613
break;
597614

598615
case MC_INT_SECERR_SEC:
599-
status_reg = MC_ERR_SEC_STATUS;
600-
addr_reg = MC_ERR_SEC_ADR;
616+
status_reg = mc->soc->regs->err_sec_status;
617+
addr_reg = mc->soc->regs->err_sec_add;
601618
break;
602619

603620
case MC_INT_DECERR_MTS:
604-
status_reg = MC_ERR_MTS_STATUS;
605-
addr_reg = MC_ERR_MTS_ADR;
621+
status_reg = mc->soc->regs->err_mts_status;
622+
addr_reg = mc->soc->regs->err_mts_add;
606623
break;
607624

608625
case MC_INT_DECERR_GENERALIZED_CARVEOUT:
609-
status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS;
610-
addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR;
626+
status_reg = mc->soc->regs->err_gen_co_status;
627+
addr_reg = mc->soc->regs->err_gen_co_add;
611628
break;
612629

613630
case MC_INT_DECERR_ROUTE_SANITY:
614-
status_reg = MC_ERR_ROUTE_SANITY_STATUS;
615-
addr_reg = MC_ERR_ROUTE_SANITY_ADR;
631+
status_reg = mc->soc->regs->err_route_status;
632+
addr_reg = mc->soc->regs->err_route_add;
616633
break;
617634

618635
default:
619-
status_reg = MC_ERR_STATUS;
620-
addr_reg = MC_ERR_ADR;
636+
status_reg = mc->soc->regs->err_status;
637+
addr_reg = mc->soc->regs->err_add;
621638

622639
#ifdef CONFIG_PHYS_ADDR_T_64BIT
623640
if (mc->soc->has_addr_hi_reg)
624-
addr_hi_reg = MC_ERR_ADR_HI;
641+
addr_hi_reg = mc->soc->regs->err_add_hi;
625642
#endif
626643
break;
627644
}
@@ -874,7 +891,7 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)
874891
unsigned int i;
875892
u32 value;
876893

877-
value = mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE);
894+
value = mc_ch_readl(mc, 0, mc->soc->regs->cfg_channel_enable);
878895
if (value <= 0) {
879896
mc->num_channels = mc->soc->num_channels;
880897
return;

‎drivers/memory/tegra/mc.h‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* SPDX-License-Identifier: GPL-2.0-only */
22
/*
3-
* Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#ifndef MEMORY_TEGRA_MC_H
@@ -14,8 +14,6 @@
1414

1515
#define MC_INTSTATUS 0x00
1616
#define MC_INTMASK 0x04
17-
#define MC_ERR_STATUS 0x08
18-
#define MC_ERR_ADR 0x0c
1917
#define MC_GART_ERROR_REQ 0x30
2018
#define MC_EMEM_ADR_CFG 0x54
2119
#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
@@ -43,19 +41,7 @@
4341
#define MC_EMEM_ARB_OVERRIDE 0xe8
4442
#define MC_TIMING_CONTROL_DBG 0xf8
4543
#define MC_TIMING_CONTROL 0xfc
46-
#define MC_ERR_VPR_STATUS 0x654
47-
#define MC_ERR_VPR_ADR 0x658
48-
#define MC_ERR_SEC_STATUS 0x67c
49-
#define MC_ERR_SEC_ADR 0x680
50-
#define MC_ERR_MTS_STATUS 0x9b0
51-
#define MC_ERR_MTS_ADR 0x9b4
52-
#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0
53-
#define MC_ERR_ROUTE_SANITY_ADR 0x9c4
54-
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
55-
#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
56-
#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8
5744
#define MC_GLOBAL_INTSTATUS 0xf24
58-
#define MC_ERR_ADR_HI 0x11fc
5945

6046
#define MC_INT_DECERR_ROUTE_SANITY BIT(20)
6147
#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17)

‎drivers/memory/tegra/tegra114.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <linux/of.h>
@@ -1114,4 +1114,5 @@ const struct tegra_mc_soc tegra114_mc_soc = {
11141114
.resets = tegra114_mc_resets,
11151115
.num_resets = ARRAY_SIZE(tegra114_mc_resets),
11161116
.ops = &tegra30_mc_ops,
1117+
.regs = &tegra20_mc_regs,
11171118
};

‎drivers/memory/tegra/tegra124.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <linux/of.h>
@@ -1275,6 +1275,7 @@ const struct tegra_mc_soc tegra124_mc_soc = {
12751275
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
12761276
.icc_ops = &tegra124_mc_icc_ops,
12771277
.ops = &tegra30_mc_ops,
1278+
.regs = &tegra20_mc_regs,
12781279
};
12791280
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
12801281

@@ -1307,5 +1308,6 @@ const struct tegra_mc_soc tegra132_mc_soc = {
13071308
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
13081309
.icc_ops = &tegra124_mc_icc_ops,
13091310
.ops = &tegra30_mc_ops,
1311+
.regs = &tegra20_mc_regs,
13101312
};
13111313
#endif /* CONFIG_ARCH_TEGRA_132_SOC */

‎drivers/memory/tegra/tegra186.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2017-2025 NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <linux/io.h>
@@ -914,5 +914,6 @@ const struct tegra_mc_soc tegra186_mc_soc = {
914914
.ops = &tegra186_mc_ops,
915915
.ch_intmask = 0x0000000f,
916916
.global_intstatus_channel_shift = 0,
917+
.regs = &tegra20_mc_regs,
917918
};
918919
#endif

‎drivers/memory/tegra/tegra194.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <soc/tegra/mc.h>
@@ -1358,4 +1358,5 @@ const struct tegra_mc_soc tegra194_mc_soc = {
13581358
.icc_ops = &tegra_mc_icc_ops,
13591359
.ch_intmask = 0x00000f00,
13601360
.global_intstatus_channel_shift = 8,
1361+
.regs = &tegra20_mc_regs,
13611362
};

‎drivers/memory/tegra/tegra20.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2012-2026 NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <linux/bitfield.h>
@@ -778,4 +778,5 @@ const struct tegra_mc_soc tegra20_mc_soc = {
778778
.num_resets = ARRAY_SIZE(tegra20_mc_resets),
779779
.icc_ops = &tegra20_mc_icc_ops,
780780
.ops = &tegra20_mc_ops,
781+
.regs = &tegra20_mc_regs,
781782
};

‎drivers/memory/tegra/tegra210.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2015-2026 NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <dt-bindings/memory/tegra210-mc.h>
@@ -1287,4 +1287,5 @@ const struct tegra_mc_soc tegra210_mc_soc = {
12871287
.resets = tegra210_mc_resets,
12881288
.num_resets = ARRAY_SIZE(tegra210_mc_resets),
12891289
.ops = &tegra30_mc_ops,
1290+
.regs = &tegra20_mc_regs,
12901291
};

‎drivers/memory/tegra/tegra234.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2022-2026, NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <soc/tegra/mc.h>
@@ -1152,4 +1152,5 @@ const struct tegra_mc_soc tegra234_mc_soc = {
11521152
* supported.
11531153
*/
11541154
.num_carveouts = 32,
1155+
.regs = &tegra20_mc_regs,
11551156
};

‎drivers/memory/tegra/tegra30.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <linux/device.h>
@@ -1400,4 +1400,5 @@ const struct tegra_mc_soc tegra30_mc_soc = {
14001400
.num_resets = ARRAY_SIZE(tegra30_mc_resets),
14011401
.icc_ops = &tegra30_mc_icc_ops,
14021402
.ops = &tegra30_mc_ops,
1403+
.regs = &tegra20_mc_regs,
14031404
};

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