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soc: renesas: rz-sysc: Add SoC identification for RZ/G3L SoC
Add SoC identification for the RZ/G3L SoC using the System Controller (SYSC) block. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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‎drivers/soc/renesas/Kconfig‎

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@@ -390,6 +390,14 @@ config ARCH_R9A08G045
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help
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This enables support for the Renesas RZ/G3S SoC variants.
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config ARCH_R9A08G046
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bool "ARM64 Platform support for R9A08G046 (RZ/G3L)"
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default y if ARCH_RENESAS
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select ARCH_RZG2L
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select SYSC_R9A08G046
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help
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This enables support for the Renesas RZ/G3L SoC variants.
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config ARCH_R9A09G011
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bool "ARM64 Platform support for R9A09G011 (RZ/V2M)"
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default y if ARCH_RENESAS
@@ -474,6 +482,10 @@ config SYSC_R9A08G045
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bool "Renesas System controller support for R9A08G045 (RZ/G3S)" if COMPILE_TEST
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select SYSC_RZ
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config SYSC_R9A08G046
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bool "Renesas System controller support for R9A08G046 (RZ/G3L)" if COMPILE_TEST
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select SYSC_RZ
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config SYS_R9A09G047
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bool "Renesas System controller support for R9A09G047 (RZ/G3E)" if COMPILE_TEST
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select SYSC_RZ

‎drivers/soc/renesas/Makefile‎

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@@ -7,6 +7,7 @@ ifdef CONFIG_SMP
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obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o
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endif
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obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o
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obj-$(CONFIG_SYSC_R9A08G046) += r9a08g046-sysc.o
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obj-$(CONFIG_SYS_R9A09G047) += r9a09g047-sys.o
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obj-$(CONFIG_SYS_R9A09G056) += r9a09g056-sys.o
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obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o

‎drivers/soc/renesas/r9a08g046-sysc.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G3L System controller (SYSC) driver
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*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*/
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include "rz-sysc.h"
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#define SYS_XSPI_MAP_STAADD_CS0 0x348
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#define SYS_XSPI_MAP_ENDADD_CS0 0x34c
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#define SYS_XSPI_MAP_STAADD_CS1 0x350
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#define SYS_XSPI_MAP_ENDADD_CS1 0x354
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#define SYS_GETH0_CFG 0x380
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#define SYS_GETH1_CFG 0x390
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#define SYS_PCIE_CFG 0x3a0
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#define SYS_PCIE_MON 0x3a4
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#define SYS_PCIE_PHY 0x3b4
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#define SYS_I2C0_CFG 0x400
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#define SYS_I2C1_CFG 0x410
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#define SYS_I2C2_CFG 0x420
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#define SYS_I2C3_CFG 0x430
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#define SYS_I3C_CFG 0x440
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#define SYS_PWRRDY_N 0xd70
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#define SYS_IPCONT_SEL_CLONECH 0xe2c
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static bool rzg3l_regmap_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case SYS_XSPI_MAP_STAADD_CS0:
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case SYS_XSPI_MAP_ENDADD_CS0:
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case SYS_XSPI_MAP_STAADD_CS1:
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case SYS_XSPI_MAP_ENDADD_CS1:
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case SYS_GETH0_CFG:
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case SYS_GETH1_CFG:
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case SYS_PCIE_CFG:
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case SYS_PCIE_MON:
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case SYS_PCIE_PHY:
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case SYS_I2C0_CFG:
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case SYS_I2C1_CFG:
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case SYS_I2C2_CFG:
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case SYS_I2C3_CFG:
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case SYS_I3C_CFG:
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case SYS_PWRRDY_N:
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case SYS_IPCONT_SEL_CLONECH:
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return true;
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default:
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return false;
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}
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}
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static bool rzg3l_regmap_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case SYS_XSPI_MAP_STAADD_CS0:
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case SYS_XSPI_MAP_ENDADD_CS0:
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case SYS_XSPI_MAP_STAADD_CS1:
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case SYS_XSPI_MAP_ENDADD_CS1:
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case SYS_PCIE_CFG:
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case SYS_PCIE_PHY:
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case SYS_I2C0_CFG:
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case SYS_I2C1_CFG:
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case SYS_I2C2_CFG:
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case SYS_I2C3_CFG:
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case SYS_I3C_CFG:
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case SYS_PWRRDY_N:
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case SYS_IPCONT_SEL_CLONECH:
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return true;
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default:
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return false;
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}
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}
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static const struct rz_sysc_soc_id_init_data rzg3l_sysc_soc_id_init_data __initconst = {
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.family = "RZ/G3L",
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.id = 0x87d9447,
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.devid_offset = 0xa04,
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.revision_mask = GENMASK(31, 28),
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.specific_id_mask = GENMASK(27, 0),
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};
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const struct rz_sysc_init_data rzg3l_sysc_init_data __initconst = {
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.soc_id_init_data = &rzg3l_sysc_soc_id_init_data,
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.readable_reg = rzg3l_regmap_readable_reg,
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.writeable_reg = rzg3l_regmap_writeable_reg,
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.max_register = 0xe2c,
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};

‎drivers/soc/renesas/rz-sysc.c‎

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@@ -88,6 +88,9 @@ static const struct of_device_id rz_sysc_match[] = {
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#ifdef CONFIG_SYSC_R9A08G045
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{ .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data },
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#endif
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#ifdef CONFIG_SYSC_R9A08G046
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{ .compatible = "renesas,r9a08g046-sysc", .data = &rzg3l_sysc_init_data },
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#endif
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#ifdef CONFIG_SYS_R9A09G047
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{ .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sys_init_data },
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#endif

‎drivers/soc/renesas/rz-sysc.h‎

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@@ -46,6 +46,7 @@ struct rz_sysc_init_data {
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};
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extern const struct rz_sysc_init_data rzg3e_sys_init_data;
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extern const struct rz_sysc_init_data rzg3l_sysc_init_data;
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extern const struct rz_sysc_init_data rzg3s_sysc_init_data;
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extern const struct rz_sysc_init_data rzv2h_sys_init_data;
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extern const struct rz_sysc_init_data rzv2n_sys_init_data;

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