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torvaldstorvalds
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Merge tag 'for-linus' of https://github.com/openrisc/linux
Pull OpenRISC updates from Stafford Horne: "The main focus for this series has been to improve OpenRISC kernel out-of-the-box support for FPGA dev boards. - Add device tree configurations for De0 Nano single and multicore configurations - Fix bug in OpenRISC SMP preventing the kernel from running on FPGA boards, due to IPIs not being unmasked on secondary CPUs in some configurations - Pick up a fix from Brian Masney defining the nop() macro to fix build failures on OpenRISC for drivers using it" * tag 'for-linus' of https://github.com/openrisc/linux: openrisc: define arch-specific version of nop() openrisc: dts: Add de0 nano multicore config and devicetree openrisc: dts: Split simple smp dts to dts and dtsi openrisc: Fix IPIs on simple multicore systems openrisc: dts: Add de0 nano config and devicetree
2 parents 8c0901b + 0dfffa5 commit a67594c

13 files changed

Lines changed: 385 additions & 14 deletions

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‎arch/openrisc/boot/dts/de0-nano-common.dtsi‎

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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/gpio/gpio.h>
4+
#include <dt-bindings/leds/common.h>
5+
6+
/ {
7+
leds0: leds {
8+
compatible = "gpio-leds";
9+
10+
led-heartbeat {
11+
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
12+
color = <LED_COLOR_ID_GREEN>;
13+
function = LED_FUNCTION_HEARTBEAT;
14+
linux,default-trigger = "heartbeat";
15+
label = "heartbeat";
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};
17+
};
18+
19+
memory@0 {
20+
device_type = "memory";
21+
reg = <0x00000000 0x02000000>;
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};
23+
24+
/* 8 Green LEDs */
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gpio0: gpio@91000000 {
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compatible = "opencores,gpio";
27+
reg = <0x91000000 0x1>, <0x91000001 0x1>;
28+
reg-names = "dat", "dirout";
29+
gpio-controller;
30+
#gpio-cells = <2>;
31+
};
32+
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/* 4 DIP Switches */
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gpio1: gpio@92000000 {
35+
compatible = "opencores,gpio";
36+
reg = <0x92000000 0x1>, <0x92000001 0x1>;
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reg-names = "dat", "dirout";
38+
gpio-controller;
39+
#gpio-cells = <2>;
40+
status = "disabled";
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};
42+
};

‎arch/openrisc/boot/dts/de0-nano-multicore.dts‎

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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/dts-v1/;
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#include "simple-smp.dtsi"
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#include "de0-nano-common.dtsi"
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/ {
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model = "Terasic DE0 Nano - Multicore";
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};
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&cpu0 {
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clock-frequency = <50000000>;
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};
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&cpu1 {
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clock-frequency = <50000000>;
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};
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&serial0 {
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clock-frequency = <50000000>;
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};

‎arch/openrisc/boot/dts/de0-nano.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "de0-nano-common.dtsi"
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/ {
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model = "Terasic DE0 Nano";
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compatible = "opencores,or1ksim";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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aliases {
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uart0 = &serial0;
16+
};
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chosen {
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stdout-path = "uart0:115200";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <0>;
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clock-frequency = <50000000>;
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};
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};
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/*
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* OR1K PIC is built into CPU and accessed via special purpose
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* registers. It is not addressable and, hence, has no 'reg'
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* property.
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*/
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pic: pic {
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compatible = "opencores,or1k-pic";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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serial0: serial@90000000 {
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compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
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reg = <0x90000000 0x100>;
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interrupts = <2>;
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clock-frequency = <50000000>;
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};
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};
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&gpio1 {
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status = "okay";
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};

‎arch/openrisc/boot/dts/simple-smp.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "simple-smp.dtsi"
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/ {
8+
model = "Simple SMP Board";
9+
};
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&cpu0 {
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clock-frequency = <20000000>;
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};
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15+
&cpu1 {
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clock-frequency = <20000000>;
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};
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&enet0 {
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status = "okay";
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};
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&serial0 {
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clock-frequency = <20000000>;
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};

arch/openrisc/boot/dts/simple_smp.dts renamed to arch/openrisc/boot/dts/simple-smp.dtsi

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@@ -1,4 +1,3 @@
1-
/dts-v1/;
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/ {
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compatible = "opencores,or1ksim";
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#address-cells = <1>;
@@ -22,15 +21,15 @@
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
25-
cpu@0 {
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cpu0: cpu@0 {
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compatible = "opencores,or1200-rtlsvn481";
2727
reg = <0>;
28-
clock-frequency = <20000000>;
2928
};
30-
cpu@1 {
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30+
cpu1: cpu@1 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <1>;
33-
clock-frequency = <20000000>;
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};
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};
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@@ -57,13 +56,13 @@
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compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
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reg = <0x90000000 0x100>;
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interrupts = <2>;
60-
clock-frequency = <20000000>;
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};
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enet0: ethoc@92000000 {
6462
compatible = "opencores,ethoc";
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reg = <0x92000000 0x800>;
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interrupts = <4>;
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big-endian;
66+
status = "disabled";
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};
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};

‎arch/openrisc/configs/de0_nano_defconfig‎

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CONFIG_SYSVIPC=y
2+
CONFIG_NO_HZ=y
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CONFIG_LOG_BUF_SHIFT=14
4+
CONFIG_BLK_DEV_INITRD=y
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# CONFIG_RD_GZIP is not set
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# CONFIG_RD_LZMA is not set
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# CONFIG_RD_LZO is not set
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# CONFIG_RD_LZ4 is not set
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# CONFIG_RD_ZSTD is not set
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CONFIG_EXPERT=y
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# CONFIG_EPOLL is not set
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# CONFIG_TIMERFD is not set
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# CONFIG_EVENTFD is not set
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# CONFIG_AIO is not set
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CONFIG_BUILTIN_DTB_NAME="de0-nano"
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# CONFIG_FPU is not set
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CONFIG_HZ_100=y
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# CONFIG_BLOCK is not set
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CONFIG_SLUB_TINY=y
20+
# CONFIG_COMPAT_BRK is not set
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# CONFIG_VM_EVENT_COUNTERS is not set
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CONFIG_NET=y
23+
CONFIG_UNIX=y
24+
CONFIG_UNIX_DIAG=y
25+
CONFIG_INET=y
26+
CONFIG_IP_MULTICAST=y
27+
CONFIG_INET_UDP_DIAG=y
28+
CONFIG_INET_RAW_DIAG=y
29+
CONFIG_INET_DIAG_DESTROY=y
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# CONFIG_IPV6 is not set
31+
CONFIG_DEVTMPFS=y
32+
CONFIG_DEVTMPFS_MOUNT=y
33+
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
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# CONFIG_FW_LOADER is not set
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# CONFIG_INPUT is not set
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# CONFIG_SERIO is not set
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# CONFIG_VT is not set
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_SERIAL_8250=y
40+
CONFIG_SERIAL_8250_CONSOLE=y
41+
CONFIG_SERIAL_OF_PLATFORM=y
42+
# CONFIG_HW_RANDOM is not set
43+
CONFIG_PPS=y
44+
CONFIG_GPIO_SYSFS=y
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# CONFIG_GPIO_SYSFS_LEGACY is not set
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CONFIG_GPIO_GENERIC_PLATFORM=y
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# CONFIG_HWMON is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_NEW_LEDS=y
50+
CONFIG_LEDS_CLASS=y
51+
CONFIG_LEDS_GPIO=y
52+
CONFIG_LEDS_TRIGGERS=y
53+
CONFIG_LEDS_TRIGGER_TIMER=y
54+
CONFIG_LEDS_TRIGGER_ONESHOT=y
55+
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
56+
CONFIG_LEDS_TRIGGER_CPU=y
57+
CONFIG_LEDS_TRIGGER_ACTIVITY=y
58+
CONFIG_LEDS_TRIGGER_GPIO=y
59+
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
60+
CONFIG_LEDS_TRIGGER_TRANSIENT=y
61+
CONFIG_LEDS_TRIGGER_PANIC=y
62+
CONFIG_LEDS_TRIGGER_NETDEV=y
63+
CONFIG_LEDS_TRIGGER_PATTERN=y
64+
CONFIG_LEDS_TRIGGER_TTY=y
65+
# CONFIG_VIRTIO_MENU is not set
66+
# CONFIG_VHOST_MENU is not set
67+
# CONFIG_DNOTIFY is not set
68+
CONFIG_TMPFS=y
69+
# CONFIG_XZ_DEC_X86 is not set
70+
# CONFIG_XZ_DEC_POWERPC is not set
71+
# CONFIG_XZ_DEC_ARM is not set
72+
# CONFIG_XZ_DEC_ARMTHUMB is not set
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# CONFIG_XZ_DEC_ARM64 is not set
74+
# CONFIG_XZ_DEC_SPARC is not set
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# CONFIG_XZ_DEC_RISCV is not set
76+
CONFIG_PRINTK_TIME=y
77+
# CONFIG_DEBUG_MISC is not set
78+
# CONFIG_FTRACE is not set
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# CONFIG_RUNTIME_TESTING_MENU is not set

‎arch/openrisc/configs/de0_nano_multicore_defconfig‎

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CONFIG_LOCALVERSION="-de0nano-smp"
2+
CONFIG_SYSVIPC=y
3+
CONFIG_POSIX_MQUEUE=y
4+
CONFIG_NO_HZ=y
5+
CONFIG_LOG_BUF_SHIFT=14
6+
CONFIG_BLK_DEV_INITRD=y
7+
# CONFIG_RD_GZIP is not set
8+
# CONFIG_RD_BZIP2 is not set
9+
# CONFIG_RD_LZMA is not set
10+
# CONFIG_RD_XZ is not set
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# CONFIG_RD_LZO is not set
12+
# CONFIG_RD_LZ4 is not set
13+
CONFIG_EXPERT=y
14+
# CONFIG_EPOLL is not set
15+
# CONFIG_TIMERFD is not set
16+
# CONFIG_EVENTFD is not set
17+
# CONFIG_AIO is not set
18+
CONFIG_KALLSYMS_ALL=y
19+
CONFIG_DCACHE_WRITETHROUGH=y
20+
CONFIG_BUILTIN_DTB_NAME="de0-nano-multicore"
21+
CONFIG_OPENRISC_HAVE_INST_CMOV=y
22+
CONFIG_SMP=y
23+
CONFIG_HZ_100=y
24+
CONFIG_JUMP_LABEL=y
25+
# CONFIG_BLOCK is not set
26+
CONFIG_SLUB_TINY=y
27+
# CONFIG_COMPAT_BRK is not set
28+
# CONFIG_VM_EVENT_COUNTERS is not set
29+
CONFIG_NET=y
30+
CONFIG_PACKET=y
31+
CONFIG_UNIX=y
32+
CONFIG_UNIX_DIAG=y
33+
CONFIG_INET=y
34+
CONFIG_IP_MULTICAST=y
35+
CONFIG_TCP_CONG_ADVANCED=y
36+
# CONFIG_TCP_CONG_BIC is not set
37+
# CONFIG_TCP_CONG_CUBIC is not set
38+
# CONFIG_TCP_CONG_WESTWOOD is not set
39+
# CONFIG_TCP_CONG_HTCP is not set
40+
# CONFIG_IPV6 is not set
41+
# CONFIG_WIRELESS is not set
42+
CONFIG_DEVTMPFS=y
43+
CONFIG_DEVTMPFS_MOUNT=y
44+
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
45+
# CONFIG_FW_LOADER is not set
46+
CONFIG_NETDEVICES=y
47+
CONFIG_ETHOC=y
48+
CONFIG_MICREL_PHY=y
49+
# CONFIG_WLAN is not set
50+
# CONFIG_INPUT is not set
51+
# CONFIG_SERIO is not set
52+
# CONFIG_VT is not set
53+
# CONFIG_LEGACY_PTYS is not set
54+
CONFIG_SERIAL_8250=y
55+
CONFIG_SERIAL_8250_CONSOLE=y
56+
CONFIG_SERIAL_OF_PLATFORM=y
57+
# CONFIG_HW_RANDOM is not set
58+
CONFIG_GPIO_SYSFS=y
59+
# CONFIG_GPIO_CDEV_V1 is not set
60+
CONFIG_GPIO_GENERIC_PLATFORM=y
61+
# CONFIG_HWMON is not set
62+
# CONFIG_USB_SUPPORT is not set
63+
CONFIG_NEW_LEDS=y
64+
CONFIG_LEDS_CLASS=y
65+
CONFIG_LEDS_GPIO=y
66+
CONFIG_LEDS_TRIGGERS=y
67+
CONFIG_LEDS_TRIGGER_TIMER=y
68+
CONFIG_LEDS_TRIGGER_ONESHOT=y
69+
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
70+
CONFIG_LEDS_TRIGGER_CPU=y
71+
CONFIG_LEDS_TRIGGER_ACTIVITY=y
72+
CONFIG_LEDS_TRIGGER_GPIO=y
73+
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
74+
CONFIG_LEDS_TRIGGER_TRANSIENT=y
75+
CONFIG_LEDS_TRIGGER_PANIC=y
76+
CONFIG_LEDS_TRIGGER_NETDEV=y
77+
CONFIG_LEDS_TRIGGER_PATTERN=y
78+
CONFIG_LEDS_TRIGGER_TTY=y
79+
# CONFIG_DNOTIFY is not set
80+
CONFIG_TMPFS=y
81+
CONFIG_NFS_FS=y
82+
CONFIG_XZ_DEC=y
83+
CONFIG_PRINTK_TIME=y
84+
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
85+
CONFIG_GDB_SCRIPTS=y
86+
CONFIG_VMLINUX_MAP=y
87+
CONFIG_HARDLOCKUP_DETECTOR=y
88+
CONFIG_WQ_WATCHDOG=y
89+
CONFIG_WQ_CPU_INTENSIVE_REPORT=y
90+
CONFIG_STACKTRACE=y
91+
CONFIG_RCU_CPU_STALL_CPUTIME=y
92+
# CONFIG_RCU_TRACE is not set

‎arch/openrisc/configs/simple_smp_defconfig‎

Lines changed: 1 addition & 1 deletion
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@@ -20,7 +20,7 @@ CONFIG_SLUB=y
2020
CONFIG_SLUB_TINY=y
2121
CONFIG_MODULES=y
2222
# CONFIG_BLOCK is not set
23-
CONFIG_BUILTIN_DTB_NAME="simple_smp"
23+
CONFIG_BUILTIN_DTB_NAME="simple-smp"
2424
CONFIG_SMP=y
2525
CONFIG_HZ_100=y
2626
CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y

‎arch/openrisc/include/asm/barrier.h‎

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@@ -4,6 +4,8 @@
44

55
#define mb() asm volatile ("l.msync" ::: "memory")
66

7+
#define nop() asm volatile ("l.nop")
8+
79
#include <asm-generic/barrier.h>
810

911
#endif /* __ASM_BARRIER_H */

‎arch/openrisc/include/asm/smp.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,8 @@ extern void smp_init_cpus(void);
2020
extern void arch_send_call_function_single_ipi(int cpu);
2121
extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
2222

23-
extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
23+
extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int),
24+
unsigned int irq);
2425
extern void handle_IPI(unsigned int ipi_msg);
2526

2627
#endif /* __ASM_OPENRISC_SMP_H */

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