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Ketan Patilkrzk
Ketan Patil
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krzk
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memory: tegra: Prepare for supporting multiple intmask registers
Add a new structure for the intmask register e.g. MC_INTMASK_0 and it's mask value. Add an array of these new structures to prepare for supporting multiple intmask registers. This is done in preparation for adding support for Tegra264 which supports multiple intmask registers. Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260226163115.1152181-6-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
1 parent 2e4cfaa commit 9f26145

11 files changed

Lines changed: 125 additions & 40 deletions

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‎drivers/memory/tegra/mc.c‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -586,9 +586,9 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
586586
}
587587

588588
/* mask all interrupts to avoid flooding */
589-
status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask;
589+
status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmasks[0].mask;
590590
} else {
591-
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
591+
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask;
592592
}
593593

594594
if (!status)
@@ -969,11 +969,13 @@ static int tegra_mc_probe(struct platform_device *pdev)
969969
}
970970
}
971971

972-
if (mc->soc->num_channels)
973-
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask,
974-
MC_INTMASK);
975-
else
976-
mc_writel(mc, mc->soc->intmask, MC_INTMASK);
972+
for (i = 0; i < mc->soc->num_intmasks; i++) {
973+
if (mc->soc->num_channels)
974+
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,
975+
mc->soc->intmasks[i].reg);
976+
else
977+
mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);
978+
}
977979
}
978980

979981
if (mc->soc->reset_ops) {

‎drivers/memory/tegra/tegra114.c‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1101,15 +1101,23 @@ static const struct tegra_mc_reset tegra114_mc_resets[] = {
11011101
TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
11021102
};
11031103

1104+
static const struct tegra_mc_intmask tegra114_mc_intmasks[] = {
1105+
{
1106+
.reg = MC_INTMASK,
1107+
.mask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1108+
MC_INT_DECERR_EMEM,
1109+
},
1110+
};
1111+
11041112
const struct tegra_mc_soc tegra114_mc_soc = {
11051113
.clients = tegra114_mc_clients,
11061114
.num_clients = ARRAY_SIZE(tegra114_mc_clients),
11071115
.num_address_bits = 32,
11081116
.atom_size = 32,
11091117
.client_id_mask = 0x7f,
11101118
.smmu = &tegra114_smmu_soc,
1111-
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1112-
MC_INT_DECERR_EMEM,
1119+
.intmasks = tegra114_mc_intmasks,
1120+
.num_intmasks = ARRAY_SIZE(tegra114_mc_intmasks),
11131121
.reset_ops = &tegra_mc_reset_ops_common,
11141122
.resets = tegra114_mc_resets,
11151123
.num_resets = ARRAY_SIZE(tegra114_mc_resets),

‎drivers/memory/tegra/tegra124.c‎

Lines changed: 22 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1258,6 +1258,15 @@ static const struct tegra_smmu_soc tegra124_smmu_soc = {
12581258
.num_asids = 128,
12591259
};
12601260

1261+
static const struct tegra_mc_intmask tegra124_mc_intmasks[] = {
1262+
{
1263+
.reg = MC_INTMASK,
1264+
.mask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1265+
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1266+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1267+
},
1268+
};
1269+
12611270
const struct tegra_mc_soc tegra124_mc_soc = {
12621271
.clients = tegra124_mc_clients,
12631272
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
@@ -1267,9 +1276,8 @@ const struct tegra_mc_soc tegra124_mc_soc = {
12671276
.smmu = &tegra124_smmu_soc,
12681277
.emem_regs = tegra124_mc_emem_regs,
12691278
.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1270-
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1271-
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1272-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1279+
.intmasks = tegra124_mc_intmasks,
1280+
.num_intmasks = ARRAY_SIZE(tegra124_mc_intmasks),
12731281
.reset_ops = &tegra_mc_reset_ops_common,
12741282
.resets = tegra124_mc_resets,
12751283
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
@@ -1297,16 +1305,24 @@ static const struct tegra_smmu_soc tegra132_smmu_soc = {
12971305
.num_asids = 128,
12981306
};
12991307

1308+
static const struct tegra_mc_intmask tegra132_mc_intmasks[] = {
1309+
{
1310+
.reg = MC_INTMASK,
1311+
.mask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1312+
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1313+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1314+
},
1315+
};
1316+
13001317
const struct tegra_mc_soc tegra132_mc_soc = {
13011318
.clients = tegra124_mc_clients,
13021319
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
13031320
.num_address_bits = 34,
13041321
.atom_size = 32,
13051322
.client_id_mask = 0x7f,
13061323
.smmu = &tegra132_smmu_soc,
1307-
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1308-
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1309-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1324+
.intmasks = tegra132_mc_intmasks,
1325+
.num_intmasks = ARRAY_SIZE(tegra132_mc_intmasks),
13101326
.reset_ops = &tegra_mc_reset_ops_common,
13111327
.resets = tegra124_mc_resets,
13121328
.num_resets = ARRAY_SIZE(tegra124_mc_resets),

‎drivers/memory/tegra/tegra186.c‎

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -901,15 +901,23 @@ static const struct tegra_mc_client tegra186_mc_clients[] = {
901901
},
902902
};
903903

904+
static const struct tegra_mc_intmask tegra186_mc_intmasks[] = {
905+
{
906+
.reg = MC_INTMASK,
907+
.mask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
908+
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
909+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
910+
},
911+
};
912+
904913
const struct tegra_mc_soc tegra186_mc_soc = {
905914
.num_clients = ARRAY_SIZE(tegra186_mc_clients),
906915
.clients = tegra186_mc_clients,
907916
.num_address_bits = 40,
908917
.num_channels = 4,
909918
.client_id_mask = 0xff,
910-
.intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
911-
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
912-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
919+
.intmasks = tegra186_mc_intmasks,
920+
.num_intmasks = ARRAY_SIZE(tegra186_mc_intmasks),
913921
.ops = &tegra186_mc_ops,
914922
.ch_intmask = 0x0000000f,
915923
.global_intstatus_channel_shift = 0,

‎drivers/memory/tegra/tegra194.c‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1343,16 +1343,23 @@ static const struct tegra_mc_client tegra194_mc_clients[] = {
13431343
},
13441344
};
13451345

1346+
static const struct tegra_mc_intmask tegra194_mc_intmasks[] = {
1347+
{
1348+
.reg = MC_INTMASK,
1349+
.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
1350+
MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1351+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1352+
},
1353+
};
1354+
13461355
const struct tegra_mc_soc tegra194_mc_soc = {
13471356
.num_clients = ARRAY_SIZE(tegra194_mc_clients),
13481357
.clients = tegra194_mc_clients,
13491358
.num_address_bits = 40,
13501359
.num_channels = 16,
13511360
.client_id_mask = 0xff,
1352-
.intmask = MC_INT_DECERR_ROUTE_SANITY |
1353-
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
1354-
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1355-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1361+
.intmasks = tegra194_mc_intmasks,
1362+
.num_intmasks = ARRAY_SIZE(tegra194_mc_intmasks),
13561363
.has_addr_hi_reg = true,
13571364
.ops = &tegra186_mc_ops,
13581365
.icc_ops = &tegra_mc_icc_ops,

‎drivers/memory/tegra/tegra20.c‎

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -695,7 +695,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void *data)
695695
unsigned int bit;
696696

697697
/* mask all interrupts to avoid flooding */
698-
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
698+
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask;
699699
if (!status)
700700
return IRQ_NONE;
701701

@@ -769,13 +769,21 @@ static const struct tegra_mc_ops tegra20_mc_ops = {
769769
.probe = tegra20_mc_probe,
770770
};
771771

772+
static const struct tegra_mc_intmask tegra20_mc_intmasks[] = {
773+
{
774+
.reg = MC_INTMASK,
775+
.mask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
776+
MC_INT_DECERR_EMEM,
777+
},
778+
};
779+
772780
const struct tegra_mc_soc tegra20_mc_soc = {
773781
.clients = tegra20_mc_clients,
774782
.num_clients = ARRAY_SIZE(tegra20_mc_clients),
775783
.num_address_bits = 32,
776784
.client_id_mask = 0x3f,
777-
.intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
778-
MC_INT_DECERR_EMEM,
785+
.intmasks = tegra20_mc_intmasks,
786+
.num_intmasks = ARRAY_SIZE(tegra20_mc_intmasks),
779787
.reset_ops = &tegra20_mc_reset_ops,
780788
.resets = tegra20_mc_resets,
781789
.num_resets = ARRAY_SIZE(tegra20_mc_resets),

‎drivers/memory/tegra/tegra210.c‎

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1273,16 +1273,24 @@ static const struct tegra_mc_reset tegra210_mc_resets[] = {
12731273
TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
12741274
};
12751275

1276+
static const struct tegra_mc_intmask tegra210_mc_intmasks[] = {
1277+
{
1278+
.reg = MC_INTMASK,
1279+
.mask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1280+
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1281+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1282+
},
1283+
};
1284+
12761285
const struct tegra_mc_soc tegra210_mc_soc = {
12771286
.clients = tegra210_mc_clients,
12781287
.num_clients = ARRAY_SIZE(tegra210_mc_clients),
12791288
.num_address_bits = 34,
12801289
.atom_size = 64,
12811290
.client_id_mask = 0xff,
12821291
.smmu = &tegra210_smmu_soc,
1283-
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1284-
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1285-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1292+
.intmasks = tegra210_mc_intmasks,
1293+
.num_intmasks = ARRAY_SIZE(tegra210_mc_intmasks),
12861294
.reset_ops = &tegra_mc_reset_ops_common,
12871295
.resets = tegra210_mc_resets,
12881296
.num_resets = ARRAY_SIZE(tegra210_mc_resets),

‎drivers/memory/tegra/tegra234.c‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1132,16 +1132,23 @@ static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {
11321132
.set = tegra234_mc_icc_set,
11331133
};
11341134

1135+
static const struct tegra_mc_intmask tegra234_mc_intmasks[] = {
1136+
{
1137+
.reg = MC_INTMASK,
1138+
.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
1139+
MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1140+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1141+
},
1142+
};
1143+
11351144
const struct tegra_mc_soc tegra234_mc_soc = {
11361145
.num_clients = ARRAY_SIZE(tegra234_mc_clients),
11371146
.clients = tegra234_mc_clients,
11381147
.num_address_bits = 40,
11391148
.num_channels = 16,
11401149
.client_id_mask = 0x1ff,
1141-
.intmask = MC_INT_DECERR_ROUTE_SANITY |
1142-
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
1143-
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1144-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1150+
.intmasks = tegra234_mc_intmasks,
1151+
.num_intmasks = ARRAY_SIZE(tegra234_mc_intmasks),
11451152
.has_addr_hi_reg = true,
11461153
.ops = &tegra186_mc_ops,
11471154
.icc_ops = &tegra234_mc_icc_ops,

‎drivers/memory/tegra/tegra264.c‎

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (C) 2025, NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (C) 2025-2026, NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <dt-bindings/memory/nvidia,tegra264.h>
@@ -290,16 +290,23 @@ static const struct tegra_mc_icc_ops tegra264_mc_icc_ops = {
290290
.set = tegra264_mc_icc_set,
291291
};
292292

293+
static const struct tegra_mc_intmask tegra264_mc_intmasks[] = {
294+
{
295+
.reg = MC_INTMASK,
296+
.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
297+
MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
298+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
299+
},
300+
};
301+
293302
const struct tegra_mc_soc tegra264_mc_soc = {
294303
.num_clients = ARRAY_SIZE(tegra264_mc_clients),
295304
.clients = tegra264_mc_clients,
296305
.num_address_bits = 40,
297306
.num_channels = 16,
298307
.client_id_mask = 0x1ff,
299-
.intmask = MC_INT_DECERR_ROUTE_SANITY |
300-
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
301-
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
302-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
308+
.intmasks = tegra264_mc_intmasks,
309+
.num_intmasks = ARRAY_SIZE(tegra264_mc_intmasks),
303310
.has_addr_hi_reg = true,
304311
.ops = &tegra186_mc_ops,
305312
.icc_ops = &tegra264_mc_icc_ops,

‎drivers/memory/tegra/tegra30.c‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1384,6 +1384,14 @@ static const struct tegra_mc_icc_ops tegra30_mc_icc_ops = {
13841384
.set = tegra30_mc_icc_set,
13851385
};
13861386

1387+
static const struct tegra_mc_intmask tegra30_mc_intmasks[] = {
1388+
{
1389+
.reg = MC_INTMASK,
1390+
.mask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1391+
MC_INT_DECERR_EMEM,
1392+
},
1393+
};
1394+
13871395
const struct tegra_mc_soc tegra30_mc_soc = {
13881396
.clients = tegra30_mc_clients,
13891397
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
@@ -1393,8 +1401,8 @@ const struct tegra_mc_soc tegra30_mc_soc = {
13931401
.smmu = &tegra30_smmu_soc,
13941402
.emem_regs = tegra30_mc_emem_regs,
13951403
.num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs),
1396-
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1397-
MC_INT_DECERR_EMEM,
1404+
.intmasks = tegra30_mc_intmasks,
1405+
.num_intmasks = ARRAY_SIZE(tegra30_mc_intmasks),
13981406
.reset_ops = &tegra_mc_reset_ops_common,
13991407
.resets = tegra30_mc_resets,
14001408
.num_resets = ARRAY_SIZE(tegra30_mc_resets),

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