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Ulf Hansson
committed
pmdomain: Merge branch fixes into next
Merge the pmdomain fixes for v7.0-rc[n] into the next branch, to allow them to get tested together with the pmdomain changes that are targeted for the next release. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2 parents cb400df + e91d5f9 commit 9d862cc

3 files changed

Lines changed: 4 additions & 85 deletions

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‎drivers/firmware/thead,th1520-aon.c‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -170,10 +170,9 @@ int th1520_aon_power_update(struct th1520_aon_chan *aon_chan, u16 rsrc,
170170
hdr->func = TH1520_AON_PM_FUNC_SET_RESOURCE_POWER_MODE;
171171
hdr->size = TH1520_AON_RPC_MSG_NUM;
172172

173-
RPC_SET_BE16(&msg.resource, 0, rsrc);
174-
RPC_SET_BE16(&msg.resource, 2,
175-
(power_on ? TH1520_AON_PM_PW_MODE_ON :
176-
TH1520_AON_PM_PW_MODE_OFF));
173+
msg.resource = cpu_to_be16(rsrc);
174+
msg.mode = cpu_to_be16(power_on ? TH1520_AON_PM_PW_MODE_ON :
175+
TH1520_AON_PM_PW_MODE_OFF);
177176

178177
ret = th1520_aon_call_rpc(aon_chan, &msg);
179178
if (ret)

‎drivers/pmdomain/imx/imx8mp-blk-ctrl.c‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -352,9 +352,6 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
352352
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
353353
regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
354354
break;
355-
case IMX8MP_HDMIBLK_PD_HDCP:
356-
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
357-
break;
358355
case IMX8MP_HDMIBLK_PD_HRV:
359356
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
360357
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
@@ -408,9 +405,6 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
408405
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
409406
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
410407
break;
411-
case IMX8MP_HDMIBLK_PD_HDCP:
412-
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
413-
break;
414408
case IMX8MP_HDMIBLK_PD_HRV:
415409
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
416410
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
@@ -439,7 +433,7 @@ static int imx8mp_hdmi_power_notifier(struct notifier_block *nb,
439433
regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);
440434
regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);
441435
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
442-
BIT(0) | BIT(1) | BIT(10));
436+
BIT(0) | BIT(1) | BIT(10) | BIT(11));
443437
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));
444438

445439
/*

‎include/linux/firmware/thead/thead,th1520-aon.h‎

Lines changed: 0 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -97,80 +97,6 @@ struct th1520_aon_rpc_ack_common {
9797
#define RPC_GET_SVC_FLAG_ACK_TYPE(MESG) (((MESG)->svc & 0x40) >> 6)
9898
#define RPC_SET_SVC_FLAG_ACK_TYPE(MESG, ACK) ((MESG)->svc |= (ACK) << 6)
9999

100-
#define RPC_SET_BE64(MESG, OFFSET, SET_DATA) \
101-
do { \
102-
u8 *data = (u8 *)(MESG); \
103-
u64 _offset = (OFFSET); \
104-
u64 _set_data = (SET_DATA); \
105-
data[_offset + 7] = _set_data & 0xFF; \
106-
data[_offset + 6] = (_set_data & 0xFF00) >> 8; \
107-
data[_offset + 5] = (_set_data & 0xFF0000) >> 16; \
108-
data[_offset + 4] = (_set_data & 0xFF000000) >> 24; \
109-
data[_offset + 3] = (_set_data & 0xFF00000000) >> 32; \
110-
data[_offset + 2] = (_set_data & 0xFF0000000000) >> 40; \
111-
data[_offset + 1] = (_set_data & 0xFF000000000000) >> 48; \
112-
data[_offset + 0] = (_set_data & 0xFF00000000000000) >> 56; \
113-
} while (0)
114-
115-
#define RPC_SET_BE32(MESG, OFFSET, SET_DATA) \
116-
do { \
117-
u8 *data = (u8 *)(MESG); \
118-
u64 _offset = (OFFSET); \
119-
u64 _set_data = (SET_DATA); \
120-
data[_offset + 3] = (_set_data) & 0xFF; \
121-
data[_offset + 2] = (_set_data & 0xFF00) >> 8; \
122-
data[_offset + 1] = (_set_data & 0xFF0000) >> 16; \
123-
data[_offset + 0] = (_set_data & 0xFF000000) >> 24; \
124-
} while (0)
125-
126-
#define RPC_SET_BE16(MESG, OFFSET, SET_DATA) \
127-
do { \
128-
u8 *data = (u8 *)(MESG); \
129-
u64 _offset = (OFFSET); \
130-
u64 _set_data = (SET_DATA); \
131-
data[_offset + 1] = (_set_data) & 0xFF; \
132-
data[_offset + 0] = (_set_data & 0xFF00) >> 8; \
133-
} while (0)
134-
135-
#define RPC_SET_U8(MESG, OFFSET, SET_DATA) \
136-
do { \
137-
u8 *data = (u8 *)(MESG); \
138-
data[OFFSET] = (SET_DATA) & 0xFF; \
139-
} while (0)
140-
141-
#define RPC_GET_BE64(MESG, OFFSET, PTR) \
142-
do { \
143-
u8 *data = (u8 *)(MESG); \
144-
u64 _offset = (OFFSET); \
145-
*(u32 *)(PTR) = \
146-
(data[_offset + 7] | data[_offset + 6] << 8 | \
147-
data[_offset + 5] << 16 | data[_offset + 4] << 24 | \
148-
data[_offset + 3] << 32 | data[_offset + 2] << 40 | \
149-
data[_offset + 1] << 48 | data[_offset + 0] << 56); \
150-
} while (0)
151-
152-
#define RPC_GET_BE32(MESG, OFFSET, PTR) \
153-
do { \
154-
u8 *data = (u8 *)(MESG); \
155-
u64 _offset = (OFFSET); \
156-
*(u32 *)(PTR) = \
157-
(data[_offset + 3] | data[_offset + 2] << 8 | \
158-
data[_offset + 1] << 16 | data[_offset + 0] << 24); \
159-
} while (0)
160-
161-
#define RPC_GET_BE16(MESG, OFFSET, PTR) \
162-
do { \
163-
u8 *data = (u8 *)(MESG); \
164-
u64 _offset = (OFFSET); \
165-
*(u16 *)(PTR) = (data[_offset + 1] | data[_offset + 0] << 8); \
166-
} while (0)
167-
168-
#define RPC_GET_U8(MESG, OFFSET, PTR) \
169-
do { \
170-
u8 *data = (u8 *)(MESG); \
171-
*(u8 *)(PTR) = (data[OFFSET]); \
172-
} while (0)
173-
174100
/*
175101
* Defines for SC PM Power Mode
176102
*/

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