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| 1 | +// SPDX-License-Identifier: GPL-2.0-only OR MIT |
| 2 | +/** |
| 3 | + * DT overlay for enabling ICSSG0 dual EMAC on AM642 EVM |
| 4 | + * |
| 5 | + * AM642 EVM Product link: https://www.ti.com/tool/TMDS64EVM |
| 6 | + * DP83TG720 daughter card link: https://www.ti.com/tool/DP83TG720-IND-SPE-EVM |
| 7 | + * |
| 8 | + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/ |
| 9 | + */ |
| 10 | + |
| 11 | +/dts-v1/; |
| 12 | +/plugin/; |
| 13 | + |
| 14 | +#include <dt-bindings/gpio/gpio.h> |
| 15 | +#include "k3-pinctrl.h" |
| 16 | + |
| 17 | +&{/} { |
| 18 | + icssg0_eth: icssg0-eth { |
| 19 | + compatible = "ti,am642-icssg-prueth"; |
| 20 | + pinctrl-names = "default"; |
| 21 | + pinctrl-0 = <&pru_icssg0_rgmii1_pins_default>, <&pru_icssg0_rgmii2_pins_default>; |
| 22 | + sram = <&oc_sram>; |
| 23 | + |
| 24 | + dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */ |
| 25 | + <&main_pktdma 0xc101 15>, /* egress slice 0 */ |
| 26 | + <&main_pktdma 0xc102 15>, /* egress slice 0 */ |
| 27 | + <&main_pktdma 0xc103 15>, /* egress slice 0 */ |
| 28 | + <&main_pktdma 0xc104 15>, /* egress slice 1 */ |
| 29 | + <&main_pktdma 0xc105 15>, /* egress slice 1 */ |
| 30 | + <&main_pktdma 0xc106 15>, /* egress slice 1 */ |
| 31 | + <&main_pktdma 0xc107 15>, /* egress slice 1 */ |
| 32 | + <&main_pktdma 0x4100 15>, /* ingress slice 0 */ |
| 33 | + <&main_pktdma 0x4101 15>; /* ingress slice 1 */ |
| 34 | + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", |
| 35 | + "tx1-0", "tx1-1", "tx1-2", "tx1-3", |
| 36 | + "rx0", "rx1"; |
| 37 | + |
| 38 | + interrupt-parent = <&icssg0_intc>; |
| 39 | + interrupts = <24 0 2>, <25 1 3>; |
| 40 | + interrupt-names = "tx_ts0", "tx_ts1"; |
| 41 | + |
| 42 | + ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>; |
| 43 | + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", |
| 44 | + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", |
| 45 | + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", |
| 46 | + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", |
| 47 | + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", |
| 48 | + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; |
| 49 | + |
| 50 | + ti,pruss-gp-mux-sel = <2>, /* MII mode */ |
| 51 | + <2>, |
| 52 | + <2>, |
| 53 | + <2>, /* MII mode */ |
| 54 | + <2>, |
| 55 | + <2>; |
| 56 | + |
| 57 | + ti,mii-g-rt = <&icssg0_mii_g_rt>; |
| 58 | + ti,mii-rt = <&icssg0_mii_rt>; |
| 59 | + ti,iep = <&icssg0_iep0>, <&icssg0_iep1>; |
| 60 | + ti,pa-stats = <&icssg0_pa_stats>; |
| 61 | + |
| 62 | + ethernet-ports { |
| 63 | + #address-cells = <1>; |
| 64 | + #size-cells = <0>; |
| 65 | + |
| 66 | + icssg0_emac0: port@0 { |
| 67 | + reg = <0>; |
| 68 | + phy-handle = <&icssg0_phy00>; |
| 69 | + phy-mode = "rgmii-id"; |
| 70 | + ti,syscon-rgmii-delay = <&main_conf 0x4100>; |
| 71 | + /* Filled in by bootloader */ |
| 72 | + local-mac-address = [00 00 00 00 00 00]; |
| 73 | + }; |
| 74 | + |
| 75 | + icssg0_emac1: port@1 { |
| 76 | + reg = <1>; |
| 77 | + phy-handle = <&icssg0_phy01>; |
| 78 | + phy-mode = "rgmii-id"; |
| 79 | + ti,syscon-rgmii-delay = <&main_conf 0x4104>; |
| 80 | + /* Filled in by bootloader */ |
| 81 | + local-mac-address = [00 00 00 00 00 00]; |
| 82 | + }; |
| 83 | + }; |
| 84 | + }; |
| 85 | +}; |
| 86 | + |
| 87 | +&main_pmx0 { |
| 88 | + pru_icssg0_mdio_pins_default: pru-icssg0-mdio-pins { |
| 89 | + pinctrl-single,pins = < |
| 90 | + /* (P3) PRG0_MDIO0_MDC */ |
| 91 | + AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) |
| 92 | + /* (P2) PRG0_MDIO0_MDIO */ |
| 93 | + AM64X_IOPAD(0x0200, PIN_INPUT, 0) |
| 94 | + /* (P16) GPIO0_32 - GPMC0_ADVn_ALE - GPIO_ETH0/1_RESETn# */ |
| 95 | + AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) |
| 96 | + >; |
| 97 | + }; |
| 98 | + |
| 99 | + pru_icssg0_rgmii1_pins_default: pru-icssg0-rgmii1-pins { |
| 100 | + pinctrl-single,pins = < |
| 101 | + AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */ |
| 102 | + AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */ |
| 103 | + AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */ |
| 104 | + AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */ |
| 105 | + AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */ |
| 106 | + AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */ |
| 107 | + AM64X_IOPAD(0x018c, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */ |
| 108 | + AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */ |
| 109 | + AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */ |
| 110 | + AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */ |
| 111 | + AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */ |
| 112 | + AM64X_IOPAD(0x019c, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */ |
| 113 | + >; |
| 114 | + }; |
| 115 | + |
| 116 | + pru_icssg0_rgmii2_pins_default: pru-icssg0-rgmii2-pins { |
| 117 | + pinctrl-single,pins = < |
| 118 | + AM64X_IOPAD(0x01b0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */ |
| 119 | + AM64X_IOPAD(0x01b4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */ |
| 120 | + AM64X_IOPAD(0x01b8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */ |
| 121 | + AM64X_IOPAD(0x01bc, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */ |
| 122 | + AM64X_IOPAD(0x01c8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */ |
| 123 | + AM64X_IOPAD(0x01c0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */ |
| 124 | + AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */ |
| 125 | + AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */ |
| 126 | + AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */ |
| 127 | + AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */ |
| 128 | + AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */ |
| 129 | + AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */ |
| 130 | + >; |
| 131 | + }; |
| 132 | + |
| 133 | + icssg0_iep0_pins_default: icssg0-iep0-pins { |
| 134 | + pinctrl-single,pins = < |
| 135 | + AM64X_IOPAD(0x01ac, PIN_OUTPUT, 2) /* (W1) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */ |
| 136 | + >; |
| 137 | + }; |
| 138 | +}; |
| 139 | + |
| 140 | +&icssg0_mdio { |
| 141 | + status = "okay"; |
| 142 | + pinctrl-names = "default"; |
| 143 | + pinctrl-0 = <&pru_icssg0_mdio_pins_default>; |
| 144 | + #address-cells = <1>; |
| 145 | + #size-cells = <0>; |
| 146 | + |
| 147 | + icssg0_phy00: ethernet-phy@0 { |
| 148 | + reg = <0x0>; |
| 149 | + }; |
| 150 | + |
| 151 | + icssg0_phy01: ethernet-phy@a { |
| 152 | + reg = <0xa>; |
| 153 | + }; |
| 154 | +}; |
| 155 | + |
| 156 | +&icssg0_iep0 { |
| 157 | + pinctrl-names = "default"; |
| 158 | + pinctrl-0 = <&icssg0_iep0_pins_default>; |
| 159 | +}; |
| 160 | + |
| 161 | +&main_gpio0 { |
| 162 | + phy-line-hog { |
| 163 | + gpio-hog; |
| 164 | + gpios = <32 GPIO_ACTIVE_HIGH>; |
| 165 | + output-high; |
| 166 | + line-name = "phy-hog-line"; |
| 167 | + }; |
| 168 | +}; |
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