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Merge tag 'tegra-for-7.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
soc/tegra: Changes for v7.1-rc1 A number of fixes went into this for the PMC and CBB drivers. The PMC driver also gains support for Tegra264 and a Kconfig symbol for the upcoming Tegra238 is added. The various per-generation Kconfig symbols are now also enabled by default for ARCH_TEGRA in order to reduce the number of configuration options that need to be explicitly enabled. * tag 'tegra-for-7.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: MAINTAINERS: Change email address for Thierry Reding soc/tegra: pmc: Add IO pads for Tegra264 soc/tegra: pmc: Rename has_impl_33v_pwr flag soc/tegra: pmc: Refactor IO pad voltage control soc/tegra: pmc: Add Tegra264 wake events soc/tegra: pmc: Add AOWAKE regs for Tegra264 soc/tegra: pmc: Add support for SoC specific AOWAKE offsets soc/tegra: pmc: Remove unused AOWAKE definitions soc/tegra: pmc: Add kerneldoc for wake-up variables soc/tegra: pmc: Correct function names in kerneldoc soc/tegra: pmc: Add kerneldoc for reboot notifier soc/tegra: common: Add Tegra114 support to devm_tegra_core_dev_init_opp_table soc/tegra: pmc: Enable core domain support for Tegra114 soc/tegra: cbb: Fix cross-fabric target timeout lookup soc/tegra: cbb: Fix incorrect ARRAY_SIZE in fabric lookup tables soc/tegra: cbb: Set ERD on resume for err interrupt soc/tegra: cbb: Add support for CBB fabrics in Tegra238 soc/tegra: Add Tegra238 Kconfig symbol soc/tegra: Make ARCH_TEGRA_SOC_FOO defaults for NVIDIA Tegra Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 84a5fe2 + 4b23feb commit 86f9823

5 files changed

Lines changed: 612 additions & 260 deletions

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‎MAINTAINERS‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -8649,7 +8649,7 @@ F: drivers/phy/mediatek/phy-mtk-hdmi*
86498649
F: drivers/phy/mediatek/phy-mtk-mipi*
86508650

86518651
DRM DRIVERS FOR NVIDIA TEGRA
8652-
M: Thierry Reding <thierry.reding@gmail.com>
8652+
M: Thierry Reding <thierry.reding@kernel.org>
86538653
M: Mikko Perttunen <mperttunen@nvidia.com>
86548654
L: dri-devel@lists.freedesktop.org
86558655
L: linux-tegra@vger.kernel.org
@@ -20247,7 +20247,7 @@ S: Maintained
2024720247
F: drivers/pci/controller/*mvebu*
2024820248

2024920249
PCI DRIVER FOR NVIDIA TEGRA
20250-
M: Thierry Reding <thierry.reding@gmail.com>
20250+
M: Thierry Reding <thierry.reding@kernel.org>
2025120251
L: linux-tegra@vger.kernel.org
2025220252
L: linux-pci@vger.kernel.org
2025320253
S: Supported
@@ -25951,7 +25951,7 @@ F: include/linux/tee_drv.h
2595125951
F: include/uapi/linux/tee.h
2595225952

2595325953
TEGRA ARCHITECTURE SUPPORT
25954-
M: Thierry Reding <thierry.reding@gmail.com>
25954+
M: Thierry Reding <thierry.reding@kernel.org>
2595525955
M: Jonathan Hunter <jonathanh@nvidia.com>
2595625956
L: linux-tegra@vger.kernel.org
2595725957
S: Supported
@@ -25983,7 +25983,7 @@ S: Supported
2598325983
F: drivers/i2c/busses/i2c-tegra.c
2598425984

2598525985
TEGRA IOMMU DRIVERS
25986-
M: Thierry Reding <thierry.reding@gmail.com>
25986+
M: Thierry Reding <thierry.reding@kernel.org>
2598725987
R: Krishna Reddy <vdumpa@nvidia.com>
2598825988
L: linux-tegra@vger.kernel.org
2598925989
S: Supported
@@ -26004,12 +26004,12 @@ F: Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml
2600426004
F: drivers/mtd/nand/raw/tegra_nand.c
2600526005

2600626006
TEGRA PWM DRIVER
26007-
M: Thierry Reding <thierry.reding@gmail.com>
26007+
M: Thierry Reding <thierry.reding@kernel.org>
2600826008
S: Supported
2600926009
F: drivers/pwm/pwm-tegra.c
2601026010

2601126011
TEGRA QUAD SPI DRIVER
26012-
M: Thierry Reding <thierry.reding@gmail.com>
26012+
M: Thierry Reding <thierry.reding@kernel.org>
2601326013
M: Jonathan Hunter <jonathanh@nvidia.com>
2601426014
M: Sowjanya Komatineni <skomatineni@nvidia.com>
2601526015
L: linux-tegra@vger.kernel.org
@@ -26027,7 +26027,7 @@ S: Supported
2602726027
F: drivers/spi/spi-tegra*
2602826028

2602926029
TEGRA VIDEO DRIVER
26030-
M: Thierry Reding <thierry.reding@gmail.com>
26030+
M: Thierry Reding <thierry.reding@kernel.org>
2603126031
M: Jonathan Hunter <jonathanh@nvidia.com>
2603226032
M: Sowjanya Komatineni <skomatineni@nvidia.com>
2603326033
M: Luca Ceresoli <luca.ceresoli@bootlin.com>

‎drivers/soc/tegra/Kconfig‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ if ARM
66

77
config ARCH_TEGRA_2x_SOC
88
bool "Enable support for Tegra20 family"
9+
default ARCH_TEGRA
910
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
1011
select ARM_ERRATA_720789
1112
select ARM_ERRATA_754327 if SMP
@@ -23,6 +24,7 @@ config ARCH_TEGRA_2x_SOC
2324

2425
config ARCH_TEGRA_3x_SOC
2526
bool "Enable support for Tegra30 family"
27+
default ARCH_TEGRA
2628
select ARM_ERRATA_754322
2729
select ARM_ERRATA_764369 if SMP
2830
select PINCTRL_TEGRA30
@@ -37,6 +39,7 @@ config ARCH_TEGRA_3x_SOC
3739

3840
config ARCH_TEGRA_114_SOC
3941
bool "Enable support for Tegra114 family"
42+
default ARCH_TEGRA
4043
select ARM_ERRATA_798181 if SMP
4144
select HAVE_ARM_ARCH_TIMER
4245
select PINCTRL_TEGRA114
@@ -49,6 +52,7 @@ config ARCH_TEGRA_114_SOC
4952

5053
config ARCH_TEGRA_124_SOC
5154
bool "Enable support for Tegra124 family"
55+
default ARCH_TEGRA
5256
select HAVE_ARM_ARCH_TIMER
5357
select PINCTRL_TEGRA124
5458
select SOC_TEGRA_FLOWCTRL
@@ -65,6 +69,7 @@ if ARM64
6569

6670
config ARCH_TEGRA_132_SOC
6771
bool "NVIDIA Tegra132 SoC"
72+
default ARCH_TEGRA
6873
select PINCTRL_TEGRA124
6974
select SOC_TEGRA_FLOWCTRL
7075
select SOC_TEGRA_PMC
@@ -76,6 +81,7 @@ config ARCH_TEGRA_132_SOC
7681

7782
config ARCH_TEGRA_210_SOC
7883
bool "NVIDIA Tegra210 SoC"
84+
default ARCH_TEGRA
7985
select PINCTRL_TEGRA210
8086
select SOC_TEGRA_FLOWCTRL
8187
select SOC_TEGRA_PMC
@@ -95,6 +101,7 @@ config ARCH_TEGRA_210_SOC
95101

96102
config ARCH_TEGRA_186_SOC
97103
bool "NVIDIA Tegra186 SoC"
104+
default ARCH_TEGRA
98105
depends on !CPU_BIG_ENDIAN
99106
select PINCTRL_TEGRA186
100107
select MAILBOX
@@ -109,6 +116,7 @@ config ARCH_TEGRA_186_SOC
109116

110117
config ARCH_TEGRA_194_SOC
111118
bool "NVIDIA Tegra194 SoC"
119+
default ARCH_TEGRA
112120
depends on !CPU_BIG_ENDIAN
113121
select MAILBOX
114122
select PINCTRL_TEGRA194
@@ -118,20 +126,32 @@ config ARCH_TEGRA_194_SOC
118126

119127
config ARCH_TEGRA_234_SOC
120128
bool "NVIDIA Tegra234 SoC"
129+
default ARCH_TEGRA
121130
depends on !CPU_BIG_ENDIAN
122131
select MAILBOX
123132
select PINCTRL_TEGRA234
124133
select SOC_TEGRA_PMC
125134
help
126135
Enable support for the NVIDIA Tegra234 SoC.
127136

137+
config ARCH_TEGRA_238_SOC
138+
bool "NVIDIA Tegra238 SoC"
139+
default ARCH_TEGRA
140+
depends on !CPU_BIG_ENDIAN
141+
select MAILBOX
142+
select SOC_TEGRA_PMC
143+
help
144+
Enable support for the NVIDIA Tegra238 SoC.
145+
128146
config ARCH_TEGRA_241_SOC
129147
bool "NVIDIA Tegra241 SoC"
148+
default ARCH_TEGRA
130149
help
131150
Enable support for the NVIDIA Tegra241 SoC.
132151

133152
config ARCH_TEGRA_264_SOC
134153
bool "NVIDIA Tegra264 SoC"
154+
default ARCH_TEGRA
135155
depends on !CPU_BIG_ENDIAN
136156
select MAILBOX
137157
select SOC_TEGRA_PMC

‎drivers/soc/tegra/cbb/tegra234-cbb.c‎

Lines changed: 166 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,15 @@ enum tegra234_cbb_fabric_ids {
8989
T234_MAX_FABRIC_ID,
9090
};
9191

92+
enum tegra238_cbb_fabric_ids {
93+
T238_CBB_FABRIC_ID = 0,
94+
T238_AON_FABRIC_ID = 4,
95+
T238_PSC_FABRIC_ID = 5,
96+
T238_BPMP_FABRIC_ID = 6,
97+
T238_APE_FABRIC_ID = 7,
98+
T238_MAX_FABRIC_ID,
99+
};
100+
92101
enum tegra264_cbb_fabric_ids {
93102
T264_SYSTEM_CBB_FABRIC_ID,
94103
T264_TOP_0_CBB_FABRIC_ID,
@@ -313,12 +322,37 @@ static void tegra234_cbb_lookup_apbslv(struct seq_file *file, const char *target
313322
}
314323
}
315324

325+
static struct tegra234_cbb *tegra234_cbb_get_fabric(u8 fab_id)
326+
{
327+
struct tegra_cbb *entry;
328+
329+
list_for_each_entry(entry, &cbb_list, node) {
330+
struct tegra234_cbb *priv = to_tegra234_cbb(entry);
331+
332+
if (priv->fabric->fab_id == fab_id)
333+
return priv;
334+
}
335+
336+
return NULL;
337+
}
338+
316339
static void tegra234_sw_lookup_target_timeout(struct seq_file *file, struct tegra234_cbb *cbb,
317340
u8 target_id, u8 fab_id)
318341
{
319342
const struct tegra234_target_lookup *map = cbb->fabric->fab_list[fab_id].target_map;
343+
struct tegra234_cbb *target_cbb = NULL;
320344
void __iomem *addr;
321345

346+
if (fab_id == cbb->fabric->fab_id)
347+
target_cbb = cbb;
348+
else
349+
target_cbb = tegra234_cbb_get_fabric(fab_id);
350+
351+
if (!target_cbb) {
352+
dev_err(cbb->base.dev, "could not find fabric for fab_id:%d\n", fab_id);
353+
return;
354+
}
355+
322356
if (target_id >= cbb->fabric->fab_list[fab_id].max_targets) {
323357
tegra_cbb_print_err(file, "\t Invalid target_id:%d\n", target_id);
324358
return;
@@ -341,7 +375,7 @@ static void tegra234_sw_lookup_target_timeout(struct seq_file *file, struct tegr
341375
* e) Goto step-a till all bits are set.
342376
*/
343377

344-
addr = cbb->regs + map[target_id].offset;
378+
addr = target_cbb->regs + map[target_id].offset;
345379

346380
if (strstr(map[target_id].name, "AXI2APB")) {
347381
addr += APB_BLOCK_TMO_STATUS_0;
@@ -881,7 +915,7 @@ static const struct tegra234_fabric_lookup tegra234_cbb_fab_list[] = {
881915
ARRAY_SIZE(tegra234_common_target_map) },
882916
[T234_AON_FABRIC_ID] = { "aon-fabric", true,
883917
tegra234_aon_target_map,
884-
ARRAY_SIZE(tegra234_bpmp_target_map) },
918+
ARRAY_SIZE(tegra234_aon_target_map) },
885919
[T234_PSC_FABRIC_ID] = { "psc-fabric" },
886920
[T234_BPMP_FABRIC_ID] = { "bpmp-fabric", true,
887921
tegra234_bpmp_target_map,
@@ -974,6 +1008,127 @@ static const struct tegra234_cbb_fabric tegra234_sce_fabric = {
9741008
.firewall_wr_ctl = 0x288,
9751009
};
9761010

1011+
static const struct tegra234_target_lookup tegra238_ape_target_map[] = {
1012+
{ "AXI2APB", 0x00000 },
1013+
{ "AGIC", 0x15000 },
1014+
{ "AMC", 0x16000 },
1015+
{ "AST0", 0x17000 },
1016+
{ "AST1", 0x18000 },
1017+
{ "AST2", 0x19000 },
1018+
{ "CBB", 0x1A000 },
1019+
};
1020+
1021+
static const struct tegra234_target_lookup tegra238_cbb_target_map[] = {
1022+
{ "AON", 0x40000 },
1023+
{ "APE", 0x50000 },
1024+
{ "BPMP", 0x41000 },
1025+
{ "HOST1X", 0x43000 },
1026+
{ "STM", 0x44000 },
1027+
{ "CBB_CENTRAL", 0x00000 },
1028+
{ "PCIE_C0", 0x51000 },
1029+
{ "PCIE_C1", 0x47000 },
1030+
{ "PCIE_C2", 0x48000 },
1031+
{ "PCIE_C3", 0x49000 },
1032+
{ "GPU", 0x4C000 },
1033+
{ "SMMU0", 0x4D000 },
1034+
{ "SMMU1", 0x4E000 },
1035+
{ "SMMU2", 0x4F000 },
1036+
{ "PSC", 0x52000 },
1037+
{ "AXI2APB_1", 0x70000 },
1038+
{ "AXI2APB_12", 0x73000 },
1039+
{ "AXI2APB_13", 0x74000 },
1040+
{ "AXI2APB_15", 0x76000 },
1041+
{ "AXI2APB_16", 0x77000 },
1042+
{ "AXI2APB_18", 0x79000 },
1043+
{ "AXI2APB_19", 0x7A000 },
1044+
{ "AXI2APB_2", 0x7B000 },
1045+
{ "AXI2APB_23", 0x7F000 },
1046+
{ "AXI2APB_25", 0x80000 },
1047+
{ "AXI2APB_26", 0x81000 },
1048+
{ "AXI2APB_27", 0x82000 },
1049+
{ "AXI2APB_28", 0x83000 },
1050+
{ "AXI2APB_32", 0x87000 },
1051+
{ "AXI2APB_33", 0x88000 },
1052+
{ "AXI2APB_4", 0x8B000 },
1053+
{ "AXI2APB_5", 0x8C000 },
1054+
{ "AXI2APB_6", 0x93000 },
1055+
{ "AXI2APB_9", 0x90000 },
1056+
{ "AXI2APB_3", 0x91000 },
1057+
};
1058+
1059+
static const struct tegra234_fabric_lookup tegra238_cbb_fab_list[] = {
1060+
[T238_CBB_FABRIC_ID] = { "cbb-fabric", true,
1061+
tegra238_cbb_target_map,
1062+
ARRAY_SIZE(tegra238_cbb_target_map) },
1063+
[T238_AON_FABRIC_ID] = { "aon-fabric", true,
1064+
tegra234_aon_target_map,
1065+
ARRAY_SIZE(tegra234_aon_target_map) },
1066+
[T238_PSC_FABRIC_ID] = { "psc-fabric" },
1067+
[T238_BPMP_FABRIC_ID] = { "bpmp-fabric", true,
1068+
tegra234_bpmp_target_map,
1069+
ARRAY_SIZE(tegra234_bpmp_target_map) },
1070+
[T238_APE_FABRIC_ID] = { "ape-fabric", true,
1071+
tegra238_ape_target_map,
1072+
ARRAY_SIZE(tegra238_ape_target_map) },
1073+
};
1074+
1075+
static const struct tegra234_cbb_fabric tegra238_aon_fabric = {
1076+
.fab_id = T238_AON_FABRIC_ID,
1077+
.fab_list = tegra238_cbb_fab_list,
1078+
.initiator_id = tegra234_initiator_id,
1079+
.errors = tegra234_cbb_errors,
1080+
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
1081+
.err_intr_enbl = 0x7,
1082+
.err_status_clr = 0x3f,
1083+
.notifier_offset = 0x17000,
1084+
.firewall_base = 0x30000,
1085+
.firewall_ctl = 0x8f0,
1086+
.firewall_wr_ctl = 0x8e8,
1087+
};
1088+
1089+
static const struct tegra234_cbb_fabric tegra238_ape_fabric = {
1090+
.fab_id = T238_APE_FABRIC_ID,
1091+
.fab_list = tegra238_cbb_fab_list,
1092+
.initiator_id = tegra234_initiator_id,
1093+
.errors = tegra234_cbb_errors,
1094+
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
1095+
.err_intr_enbl = 0xf,
1096+
.err_status_clr = 0x3f,
1097+
.notifier_offset = 0x1E000,
1098+
.firewall_base = 0x30000,
1099+
.firewall_ctl = 0xad0,
1100+
.firewall_wr_ctl = 0xac8,
1101+
};
1102+
1103+
static const struct tegra234_cbb_fabric tegra238_bpmp_fabric = {
1104+
.fab_id = T238_BPMP_FABRIC_ID,
1105+
.fab_list = tegra238_cbb_fab_list,
1106+
.initiator_id = tegra234_initiator_id,
1107+
.errors = tegra234_cbb_errors,
1108+
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
1109+
.err_intr_enbl = 0xf,
1110+
.err_status_clr = 0x3f,
1111+
.notifier_offset = 0x19000,
1112+
.firewall_base = 0x30000,
1113+
.firewall_ctl = 0x8f0,
1114+
.firewall_wr_ctl = 0x8e8,
1115+
};
1116+
1117+
static const struct tegra234_cbb_fabric tegra238_cbb_fabric = {
1118+
.fab_id = T238_CBB_FABRIC_ID,
1119+
.fab_list = tegra238_cbb_fab_list,
1120+
.initiator_id = tegra234_initiator_id,
1121+
.errors = tegra234_cbb_errors,
1122+
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
1123+
.err_intr_enbl = 0x3f,
1124+
.err_status_clr = 0x3f,
1125+
.notifier_offset = 0x60000,
1126+
.off_mask_erd = 0x3d004,
1127+
.firewall_base = 0x10000,
1128+
.firewall_ctl = 0x2230,
1129+
.firewall_wr_ctl = 0x2228,
1130+
};
1131+
9771132
static const char * const tegra241_initiator_id[] = {
9781133
[0x0] = "TZ",
9791134
[0x1] = "CCPLEX",
@@ -1160,7 +1315,7 @@ static const struct tegra234_fabric_lookup tegra241_cbb_fab_list[] = {
11601315
[T234_CBB_FABRIC_ID] = { "cbb-fabric", true,
11611316
tegra241_cbb_target_map, ARRAY_SIZE(tegra241_cbb_target_map) },
11621317
[T234_BPMP_FABRIC_ID] = { "bpmp-fabric", true,
1163-
tegra241_bpmp_target_map, ARRAY_SIZE(tegra241_cbb_target_map) },
1318+
tegra241_bpmp_target_map, ARRAY_SIZE(tegra241_bpmp_target_map) },
11641319
};
11651320
static const struct tegra234_cbb_fabric tegra241_cbb_fabric = {
11661321
.fab_id = T234_CBB_FABRIC_ID,
@@ -1480,6 +1635,10 @@ static const struct of_device_id tegra234_cbb_dt_ids[] = {
14801635
{ .compatible = "nvidia,tegra234-dce-fabric", .data = &tegra234_dce_fabric },
14811636
{ .compatible = "nvidia,tegra234-rce-fabric", .data = &tegra234_rce_fabric },
14821637
{ .compatible = "nvidia,tegra234-sce-fabric", .data = &tegra234_sce_fabric },
1638+
{ .compatible = "nvidia,tegra238-aon-fabric", .data = &tegra238_aon_fabric },
1639+
{ .compatible = "nvidia,tegra238-ape-fabric", .data = &tegra238_ape_fabric },
1640+
{ .compatible = "nvidia,tegra238-bpmp-fabric", .data = &tegra238_bpmp_fabric },
1641+
{ .compatible = "nvidia,tegra238-cbb-fabric", .data = &tegra238_cbb_fabric },
14831642
{ .compatible = "nvidia,tegra264-sys-cbb-fabric", .data = &tegra264_sys_cbb_fabric },
14841643
{ .compatible = "nvidia,tegra264-top0-cbb-fabric", .data = &tegra264_top0_cbb_fabric },
14851644
{ .compatible = "nvidia,tegra264-uphy0-cbb-fabric", .data = &tegra264_uphy0_cbb_fabric },
@@ -1586,6 +1745,10 @@ static int __maybe_unused tegra234_cbb_resume_noirq(struct device *dev)
15861745
{
15871746
struct tegra234_cbb *cbb = dev_get_drvdata(dev);
15881747

1748+
/* set ERD bit to mask SError and generate interrupt to report error */
1749+
if (cbb->fabric->off_mask_erd)
1750+
tegra234_cbb_mask_serror(cbb);
1751+
15891752
tegra234_cbb_error_enable(&cbb->base);
15901753

15911754
dev_dbg(dev, "%s resumed\n", cbb->fabric->fab_list[cbb->fabric->fab_id].name);

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