Skip to content

Commit 86bcf7b

Browse files
torvaldstorvalds
committed
Merge tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Paul Walmsley: - Support for the RISC-V-standardized RPMI interface. RPMI is a platform management communication mechanism between OSes running on application processors, and a remote platform management processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip, mailbox, and clk changes. - Support for the RISC-V-standardized MPXY SBI extension. MPXY is a RISC-V-specific standard implementing a shared memory mailbox between S-mode operating systems (e.g., Linux) and M-mode firmware (e.g., OpenSBI). It is part of this PR since one of its use cases is to enable M-mode firmware to act as a single RPMI client for all RPMI activity on a core (including S-mode RPMI activity). Includes a mailbox driver. - Some ACPI-related updates to enable the use of RPMI and MPXY. - The addition of Linux-wide memcpy_{from,to}_le32() static inline functions, for RPMI use. - An ACPI Kconfig change to enable boot logos on any ACPI-using architecture (including RISC-V) - A RISC-V defconfig change to add GPIO keyboard and event device support, for front panel shutdown or reboot buttons * tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (26 commits) clk: COMMON_CLK_RPMI should depend on RISCV ACPI: support BGRT table on RISC-V MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers RISC-V: Enable GPIO keyboard and event device in RV64 defconfig irqchip/riscv-rpmi-sysmsi: Add ACPI support mailbox/riscv-sbi-mpxy: Add ACPI support irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode() ACPI: RISC-V: Add RPMI System MSI to GSI mapping ACPI: RISC-V: Add support to update gsi range ACPI: RISC-V: Create interrupt controller list in sorted order ACPI: scan: Update honor list for RPMI System MSI ACPI: Add support for nargs_prop in acpi_fwnode_get_reference_args() ACPI: property: Refactor acpi_fwnode_get_reference_args() to support nargs_prop irqchip: Add driver for the RPMI system MSI service group dt-bindings: Add RPMI system MSI interrupt controller bindings dt-bindings: Add RPMI system MSI message proxy bindings clk: Add clock driver for the RISC-V RPMI clock service group dt-bindings: clock: Add RPMI clock service controller bindings dt-bindings: clock: Add RPMI clock service message proxy bindings mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver ...
2 parents 7c738cb + 68247d4 commit 86bcf7b

29 files changed

Lines changed: 2981 additions & 84 deletions

‎Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,64 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/riscv,rpmi-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: RISC-V RPMI clock service group based clock controller
8+
9+
maintainers:
10+
- Anup Patel <anup@brainfault.org>
11+
12+
description: |
13+
The RISC-V Platform Management Interface (RPMI) [1] defines a
14+
messaging protocol which is modular and extensible. The supervisor
15+
software can send/receive RPMI messages via SBI MPXY extension [2]
16+
or some dedicated supervisor-mode RPMI transport.
17+
18+
The RPMI specification [1] defines clock service group for accessing
19+
system clocks managed by a platform microcontroller. The supervisor
20+
software can access RPMI clock service group via SBI MPXY channel or
21+
some dedicated supervisor-mode RPMI transport.
22+
23+
===========================================
24+
References
25+
===========================================
26+
27+
[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
28+
https://github.com/riscv-non-isa/riscv-rpmi/releases
29+
30+
[2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher)
31+
https://github.com/riscv-non-isa/riscv-sbi-doc/releases
32+
33+
properties:
34+
compatible:
35+
description:
36+
Intended for use by the supervisor software.
37+
const: riscv,rpmi-clock
38+
39+
mboxes:
40+
maxItems: 1
41+
description:
42+
Mailbox channel of the underlying RPMI transport or SBI message proxy channel.
43+
44+
"#clock-cells":
45+
const: 1
46+
description:
47+
Platform specific CLOCK_ID as defined by the RISC-V Platform Management
48+
Interface (RPMI) specification.
49+
50+
required:
51+
- compatible
52+
- mboxes
53+
- "#clock-cells"
54+
55+
additionalProperties: false
56+
57+
examples:
58+
- |
59+
clock-controller {
60+
compatible = "riscv,rpmi-clock";
61+
mboxes = <&mpxy_mbox 0x1000 0x0>;
62+
#clock-cells = <1>;
63+
};
64+
...

‎Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,64 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/riscv,rpmi-mpxy-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: RISC-V RPMI clock service group based message proxy
8+
9+
maintainers:
10+
- Anup Patel <anup@brainfault.org>
11+
12+
description: |
13+
The RISC-V Platform Management Interface (RPMI) [1] defines a
14+
messaging protocol which is modular and extensible. The supervisor
15+
software can send/receive RPMI messages via SBI MPXY extension [2]
16+
or some dedicated supervisor-mode RPMI transport.
17+
18+
The RPMI specification [1] defines clock service group for accessing
19+
system clocks managed by a platform microcontroller. The SBI implementation
20+
(machine mode firmware or hypervisor) can implement an SBI MPXY channel
21+
to allow RPMI clock service group access to the supervisor software.
22+
23+
===========================================
24+
References
25+
===========================================
26+
27+
[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
28+
https://github.com/riscv-non-isa/riscv-rpmi/releases
29+
30+
[2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher)
31+
https://github.com/riscv-non-isa/riscv-sbi-doc/releases
32+
33+
properties:
34+
compatible:
35+
description:
36+
Intended for use by the SBI implementation.
37+
const: riscv,rpmi-mpxy-clock
38+
39+
mboxes:
40+
maxItems: 1
41+
description:
42+
Mailbox channel of the underlying RPMI transport.
43+
44+
riscv,sbi-mpxy-channel-id:
45+
$ref: /schemas/types.yaml#/definitions/uint32
46+
description:
47+
The SBI MPXY channel id to be used for providing RPMI access to
48+
the supervisor software.
49+
50+
required:
51+
- compatible
52+
- mboxes
53+
- riscv,sbi-mpxy-channel-id
54+
55+
additionalProperties: false
56+
57+
examples:
58+
- |
59+
clock-service {
60+
compatible = "riscv,rpmi-mpxy-clock";
61+
mboxes = <&rpmi_shmem_mbox 0x8>;
62+
riscv,sbi-mpxy-channel-id = <0x1000>;
63+
};
64+
...

‎Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-mpxy-system-msi.yaml‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-mpxy-system-msi.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: RISC-V RPMI system MSI service group based message proxy
8+
9+
maintainers:
10+
- Anup Patel <anup@brainfault.org>
11+
12+
description: |
13+
The RISC-V Platform Management Interface (RPMI) [1] defines a
14+
messaging protocol which is modular and extensible. The supervisor
15+
software can send/receive RPMI messages via SBI MPXY extension [2]
16+
or some dedicated supervisor-mode RPMI transport.
17+
18+
The RPMI specification [1] defines system MSI service group which
19+
allow application processors to receive MSIs upon system events
20+
such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug
21+
event, memory hotplug event, etc from the platform microcontroller.
22+
The SBI implementation (machine mode firmware or hypervisor) can
23+
implement an SBI MPXY channel to allow RPMI system MSI service
24+
group access to the supervisor software.
25+
26+
===========================================
27+
References
28+
===========================================
29+
30+
[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
31+
https://github.com/riscv-non-isa/riscv-rpmi/releases
32+
33+
[2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher)
34+
https://github.com/riscv-non-isa/riscv-sbi-doc/releases
35+
36+
properties:
37+
compatible:
38+
description:
39+
Intended for use by the SBI implementation.
40+
const: riscv,rpmi-mpxy-system-msi
41+
42+
mboxes:
43+
maxItems: 1
44+
description:
45+
Mailbox channel of the underlying RPMI transport.
46+
47+
riscv,sbi-mpxy-channel-id:
48+
$ref: /schemas/types.yaml#/definitions/uint32
49+
description:
50+
The SBI MPXY channel id to be used for providing RPMI access to
51+
the supervisor software.
52+
53+
required:
54+
- compatible
55+
- mboxes
56+
- riscv,sbi-mpxy-channel-id
57+
58+
additionalProperties: false
59+
60+
examples:
61+
- |
62+
interrupt-controller {
63+
compatible = "riscv,rpmi-mpxy-system-msi";
64+
mboxes = <&rpmi_shmem_mbox 0x2>;
65+
riscv,sbi-mpxy-channel-id = <0x2000>;
66+
};
67+
...

‎Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-system-msi.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: RISC-V RPMI system MSI service group based interrupt controller
8+
9+
maintainers:
10+
- Anup Patel <anup@brainfault.org>
11+
12+
description: |
13+
The RISC-V Platform Management Interface (RPMI) [1] defines a
14+
messaging protocol which is modular and extensible. The supervisor
15+
software can send/receive RPMI messages via SBI MPXY extension [2]
16+
or some dedicated supervisor-mode RPMI transport.
17+
18+
The RPMI specification [1] defines system MSI service group which
19+
allow application processors to receive MSIs upon system events
20+
such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug
21+
event, memory hotplug event, etc from the platform microcontroller.
22+
The supervisor software can access RPMI system MSI service group via
23+
SBI MPXY channel or some dedicated supervisor-mode RPMI transport.
24+
25+
===========================================
26+
References
27+
===========================================
28+
29+
[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
30+
https://github.com/riscv-non-isa/riscv-rpmi/releases
31+
32+
[2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher)
33+
https://github.com/riscv-non-isa/riscv-sbi-doc/releases
34+
35+
allOf:
36+
- $ref: /schemas/interrupt-controller.yaml#
37+
38+
properties:
39+
compatible:
40+
description:
41+
Intended for use by the supervisor software.
42+
const: riscv,rpmi-system-msi
43+
44+
mboxes:
45+
maxItems: 1
46+
description:
47+
Mailbox channel of the underlying RPMI transport or SBI message proxy channel.
48+
49+
msi-parent: true
50+
51+
interrupt-controller: true
52+
53+
"#interrupt-cells":
54+
const: 1
55+
56+
required:
57+
- compatible
58+
- mboxes
59+
- msi-parent
60+
- interrupt-controller
61+
- "#interrupt-cells"
62+
63+
additionalProperties: false
64+
65+
examples:
66+
- |
67+
interrupt-controller {
68+
compatible = "riscv,rpmi-system-msi";
69+
mboxes = <&mpxy_mbox 0x2000 0x0>;
70+
msi-parent = <&imsic_slevel>;
71+
interrupt-controller;
72+
#interrupt-cells = <1>;
73+
};
74+
...

‎Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml‎

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,124 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: RISC-V Platform Management Interface (RPMI) shared memory mailbox
8+
9+
maintainers:
10+
- Anup Patel <anup@brainfault.org>
11+
12+
description: |
13+
The RISC-V Platform Management Interface (RPMI) [1] defines a common shared
14+
memory based RPMI transport. This RPMI shared memory transport integrates as
15+
mailbox controller in the SBI implementation or supervisor software whereas
16+
each RPMI service group is mailbox client in the SBI implementation and
17+
supervisor software.
18+
19+
===========================================
20+
References
21+
===========================================
22+
23+
[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
24+
https://github.com/riscv-non-isa/riscv-rpmi/releases
25+
26+
properties:
27+
compatible:
28+
const: riscv,rpmi-shmem-mbox
29+
30+
reg:
31+
minItems: 2
32+
items:
33+
- description: A2P request queue base address
34+
- description: P2A acknowledgment queue base address
35+
- description: P2A request queue base address
36+
- description: A2P acknowledgment queue base address
37+
- description: A2P doorbell address
38+
39+
reg-names:
40+
minItems: 2
41+
items:
42+
- const: a2p-req
43+
- const: p2a-ack
44+
- enum: [ p2a-req, a2p-doorbell ]
45+
- const: a2p-ack
46+
- const: a2p-doorbell
47+
48+
interrupts:
49+
maxItems: 1
50+
description:
51+
The RPMI shared memory transport supports P2A doorbell as a wired
52+
interrupt and this property specifies the interrupt source.
53+
54+
msi-parent:
55+
description:
56+
The RPMI shared memory transport supports P2A doorbell as a system MSI
57+
and this property specifies the target MSI controller.
58+
59+
riscv,slot-size:
60+
$ref: /schemas/types.yaml#/definitions/uint32
61+
minimum: 64
62+
description:
63+
Power-of-2 RPMI slot size of the RPMI shared memory transport.
64+
65+
riscv,a2p-doorbell-value:
66+
$ref: /schemas/types.yaml#/definitions/uint32
67+
default: 0x1
68+
description:
69+
Value written to the 32-bit A2P doorbell register.
70+
71+
riscv,p2a-doorbell-sysmsi-index:
72+
$ref: /schemas/types.yaml#/definitions/uint32
73+
description:
74+
The RPMI shared memory transport supports P2A doorbell as a system MSI
75+
and this property specifies system MSI index to be used for configuring
76+
the P2A doorbell MSI.
77+
78+
"#mbox-cells":
79+
const: 1
80+
description:
81+
The first cell specifies RPMI service group ID.
82+
83+
required:
84+
- compatible
85+
- reg
86+
- reg-names
87+
- riscv,slot-size
88+
- "#mbox-cells"
89+
90+
anyOf:
91+
- required:
92+
- interrupts
93+
- required:
94+
- msi-parent
95+
96+
additionalProperties: false
97+
98+
examples:
99+
- |
100+
// Example 1 (RPMI shared memory with only 2 queues):
101+
mailbox@10080000 {
102+
compatible = "riscv,rpmi-shmem-mbox";
103+
reg = <0x10080000 0x10000>,
104+
<0x10090000 0x10000>;
105+
reg-names = "a2p-req", "p2a-ack";
106+
msi-parent = <&imsic_mlevel>;
107+
riscv,slot-size = <64>;
108+
#mbox-cells = <1>;
109+
};
110+
- |
111+
// Example 2 (RPMI shared memory with only 4 queues):
112+
mailbox@10001000 {
113+
compatible = "riscv,rpmi-shmem-mbox";
114+
reg = <0x10001000 0x800>,
115+
<0x10001800 0x800>,
116+
<0x10002000 0x800>,
117+
<0x10002800 0x800>,
118+
<0x10003000 0x4>;
119+
reg-names = "a2p-req", "p2a-ack", "p2a-req", "a2p-ack", "a2p-doorbell";
120+
msi-parent = <&imsic_mlevel>;
121+
riscv,slot-size = <64>;
122+
riscv,a2p-doorbell-value = <0x00008000>;
123+
#mbox-cells = <1>;
124+
};

0 commit comments

Comments
 (0)