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dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
Document the SATA PHY on the EIC7700 SoC platform, describing its usage. Signed-off-by: Yulin Lu <luyulin@eswincomputing.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260205082129.1482-1-luyulin@eswincomputing.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Eswin EIC7700 SoC SATA PHY
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maintainers:
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- Yulin Lu <luyulin@eswincomputing.com>
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- Huan He <hehuan1@eswincomputing.com>
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properties:
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compatible:
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const: eswin,eic7700-sata-phy
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: phy
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: port
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- const: phy
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eswin,tx-amplitude-tuning:
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description: This adjusts the transmitter amplitude signal, and its value
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is derived from eye diagram tuning. The three values correspond to Gen1,
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Gen2, and Gen3 parameters respectively.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: Gen1 parameter.
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minimum: 0
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maximum: 0x7f
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- description: Gen2 parameter.
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minimum: 0
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maximum: 0x7f
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- description: Gen3 parameter.
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minimum: 0
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maximum: 0x7f
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default: [0, 0, 0]
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eswin,tx-preemph-tuning:
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description: This adjusts the transmitter de-emphasis signal, and its value
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is derived from eye diagram tuning. The three values correspond to Gen1,
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Gen2, and Gen3 parameters respectively.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: Gen1 parameter.
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minimum: 0
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maximum: 0x3f
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- description: Gen2 parameter.
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minimum: 0
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maximum: 0x3f
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- description: Gen3 parameter.
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minimum: 0
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maximum: 0x3f
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default: [0, 0, 0]
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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sata-phy@50440300 {
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compatible = "eswin,eic7700-sata-phy";
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reg = <0x50440300 0x40>;
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clocks = <&hspcrg 17>;
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clock-names = "phy";
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resets = <&hspcrg 0>, <&hspcrg 1>;
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reset-names = "port", "phy";
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#phy-cells = <0>;
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};

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