Skip to content

Commit 75d627e

Browse files
Fabio Estevammmind
Fabio Estevam
authored and
mmind
committed
dt-bindings: clock: rockchip: Add RV1103B CRU support
Add support for the Rockchip RV1103B Clock and Reset Unit (CRU). The RV1103B CRU is compatible with the existing RV1126B binding. Add the compatible string to the schema and introduce the corresponding clock ID definitions. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260210022620.172570-1-festevam@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
1 parent 6de23f8 commit 75d627e

2 files changed

Lines changed: 221 additions & 0 deletions

File tree

‎Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ description:
1717
properties:
1818
compatible:
1919
enum:
20+
- rockchip,rv1103b-cru
2021
- rockchip,rv1126b-cru
2122

2223
reg:

‎include/dt-bindings/clock/rockchip,rv1103b-cru.h‎

Lines changed: 220 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,220 @@
1+
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2+
/*
3+
* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
4+
* Author: Elaine Zhang <zhangqing@rock-chips.com>
5+
*/
6+
7+
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
8+
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
9+
10+
#define PLL_GPLL 0
11+
#define ARMCLK 1
12+
#define PLL_DPLL 2
13+
#define XIN_OSC0_HALF 3
14+
#define CLK_GPLL_DIV24 4
15+
#define CLK_GPLL_DIV12 5
16+
#define CLK_GPLL_DIV6 6
17+
#define CLK_GPLL_DIV4 7
18+
#define CLK_GPLL_DIV3 8
19+
#define CLK_GPLL_DIV2P5 9
20+
#define CLK_GPLL_DIV2 10
21+
#define CLK_UART0_SRC 11
22+
#define CLK_UART1_SRC 12
23+
#define CLK_UART2_SRC 13
24+
#define CLK_UART0_FRAC 14
25+
#define CLK_UART1_FRAC 15
26+
#define CLK_UART2_FRAC 16
27+
#define CLK_SAI_SRC 17
28+
#define CLK_SAI_FRAC 18
29+
#define LSCLK_NPU_SRC 19
30+
#define CLK_NPU_SRC 20
31+
#define ACLK_VEPU_SRC 21
32+
#define CLK_VEPU_SRC 22
33+
#define ACLK_VI_SRC 23
34+
#define CLK_ISP_SRC 24
35+
#define DCLK_VICAP 25
36+
#define CCLK_EMMC 26
37+
#define CCLK_SDMMC0 27
38+
#define SCLK_SFC_2X 28
39+
#define LSCLK_PERI_SRC 29
40+
#define ACLK_PERI_SRC 30
41+
#define HCLK_HPMCU 31
42+
#define SCLK_UART0 32
43+
#define SCLK_UART1 33
44+
#define SCLK_UART2 34
45+
#define CLK_I2C_PMU 35
46+
#define CLK_I2C_PERI 36
47+
#define CLK_SPI0 37
48+
#define CLK_PWM0_SRC 38
49+
#define CLK_PWM1 39
50+
#define CLK_PWM2 40
51+
#define DCLK_DECOM_SRC 41
52+
#define CCLK_SDMMC1 42
53+
#define CLK_CORE_CRYPTO 43
54+
#define CLK_PKA_CRYPTO 44
55+
#define CLK_CORE_RGA 45
56+
#define MCLK_SAI_SRC 46
57+
#define CLK_FREQ_PWM0_SRC 47
58+
#define CLK_COUNTER_PWM0_SRC 48
59+
#define PCLK_TOP_ROOT 49
60+
#define CLK_REF_MIPI0 50
61+
#define CLK_MIPI0_OUT2IO 51
62+
#define CLK_REF_MIPI1 52
63+
#define CLK_MIPI1_OUT2IO 53
64+
#define MCLK_SAI_OUT2IO 54
65+
#define ACLK_NPU_ROOT 55
66+
#define HCLK_RKNN 56
67+
#define ACLK_RKNN 57
68+
#define LSCLK_VEPU_ROOT 58
69+
#define HCLK_VEPU 59
70+
#define ACLK_VEPU 60
71+
#define CLK_CORE_VEPU 61
72+
#define PCLK_IOC_VCCIO3 62
73+
#define PCLK_ACODEC 63
74+
#define PCLK_USBPHY 64
75+
#define LSCLK_VI_100M 65
76+
#define LSCLK_VI_ROOT 66
77+
#define HCLK_ISP 67
78+
#define ACLK_ISP 68
79+
#define CLK_CORE_ISP 69
80+
#define ACLK_VICAP 70
81+
#define HCLK_VICAP 71
82+
#define ISP0CLK_VICAP 72
83+
#define PCLK_CSI2HOST0 73
84+
#define PCLK_CSI2HOST1 74
85+
#define HCLK_EMMC 75
86+
#define HCLK_SFC 76
87+
#define HCLK_SFC_XIP 77
88+
#define HCLK_SDMMC0 78
89+
#define PCLK_CSIPHY 79
90+
#define PCLK_GPIO1 80
91+
#define DBCLK_GPIO1 81
92+
#define PCLK_IOC_VCCIO47 82
93+
#define LSCLK_DDR_ROOT 83
94+
#define CLK_TIMER_DDRMON 84
95+
#define LSCLK_PMU_ROOT 85
96+
#define PCLK_PMU 86
97+
#define XIN_RC_DIV 87
98+
#define CLK_32K 88
99+
#define PCLK_PMU_GPIO0 89
100+
#define DBCLK_PMU_GPIO0 90
101+
#define CLK_DDR_FAIL_SAFE 91
102+
#define PCLK_PMU_HP_TIMER 92
103+
#define CLK_PMU_32K_HP_TIMER 93
104+
#define PCLK_PWM0 94
105+
#define CLK_PWM0 95
106+
#define CLK_OSC_PWM0 96
107+
#define CLK_RC_PWM0 97
108+
#define CLK_FREQ_PWM0 98
109+
#define CLK_COUNTER_PWM0 99
110+
#define PCLK_I2C0 100
111+
#define CLK_I2C0 101
112+
#define PCLK_UART0 102
113+
#define PCLK_IOC_PMUIO0 103
114+
#define CLK_REFOUT 104
115+
#define CLK_PREROLL 105
116+
#define CLK_PREROLL_32K 106
117+
#define CLK_LPMCU_PMU 107
118+
#define PCLK_SPI2AHB 108
119+
#define HCLK_SPI2AHB 109
120+
#define SCLK_SPI2AHB 110
121+
#define PCLK_WDT_LPMCU 111
122+
#define TCLK_WDT_LPMCU 112
123+
#define HCLK_SFC_PMU1 113
124+
#define HCLK_SFC_XIP_PMU1 114
125+
#define SCLK_SFC_2X_PMU1 115
126+
#define CLK_LPMCU 116
127+
#define CLK_LPMCU_RTC 117
128+
#define PCLK_LPMCU_MAILBOX 118
129+
#define PCLK_IOC_PMUIO1 119
130+
#define PCLK_CRU_PMU1 120
131+
#define PCLK_PERI_ROOT 121
132+
#define PCLK_RTC_ROOT 122
133+
#define CLK_TIMER_ROOT 123
134+
#define PCLK_TIMER 124
135+
#define CLK_TIMER0 125
136+
#define CLK_TIMER1 126
137+
#define CLK_TIMER2 127
138+
#define CLK_TIMER3 128
139+
#define CLK_TIMER4 129
140+
#define CLK_TIMER5 130
141+
#define PCLK_STIMER 131
142+
#define CLK_STIMER0 132
143+
#define CLK_STIMER1 133
144+
#define PCLK_WDT_NS 134
145+
#define TCLK_WDT_NS 135
146+
#define PCLK_WDT_S 136
147+
#define TCLK_WDT_S 137
148+
#define PCLK_WDT_HPMCU 138
149+
#define TCLK_WDT_HPMCU 139
150+
#define PCLK_I2C1 140
151+
#define CLK_I2C1 141
152+
#define PCLK_I2C2 142
153+
#define CLK_I2C2 143
154+
#define PCLK_I2C3 144
155+
#define CLK_I2C3 145
156+
#define PCLK_I2C4 146
157+
#define CLK_I2C4 147
158+
#define PCLK_SPI0 148
159+
#define PCLK_PWM1 149
160+
#define CLK_OSC_PWM1 150
161+
#define PCLK_PWM2 151
162+
#define CLK_OSC_PWM2 152
163+
#define PCLK_UART2 153
164+
#define PCLK_UART1 154
165+
#define ACLK_RKDMA 155
166+
#define PCLK_TSADC 156
167+
#define CLK_TSADC 157
168+
#define CLK_TSADC_TSEN 158
169+
#define PCLK_SARADC 159
170+
#define CLK_SARADC 160
171+
#define PCLK_GPIO2 161
172+
#define DBCLK_GPIO2 162
173+
#define PCLK_IOC_VCCIO6 163
174+
#define ACLK_USBOTG 164
175+
#define CLK_REF_USBOTG 165
176+
#define HCLK_SDMMC1 166
177+
#define HCLK_SAI 167
178+
#define MCLK_SAI 168
179+
#define ACLK_CRYPTO 169
180+
#define HCLK_CRYPTO 170
181+
#define HCLK_RK_RNG_NS 171
182+
#define HCLK_RK_RNG_S 172
183+
#define PCLK_OTPC_NS 173
184+
#define CLK_OTPC_ROOT_NS 174
185+
#define CLK_SBPI_OTPC_NS 175
186+
#define CLK_USER_OTPC_NS 176
187+
#define PCLK_OTPC_S 177
188+
#define CLK_OTPC_ROOT_S 178
189+
#define CLK_SBPI_OTPC_S 179
190+
#define CLK_USER_OTPC_S 180
191+
#define CLK_OTPC_ARB 181
192+
#define PCLK_OTP_MASK 182
193+
#define HCLK_RGA 183
194+
#define ACLK_RGA 184
195+
#define ACLK_MAC 185
196+
#define PCLK_MAC 186
197+
#define CLK_MACPHY 187
198+
#define ACLK_SPINLOCK 188
199+
#define HCLK_CACHE 189
200+
#define PCLK_HPMCU_MAILBOX 190
201+
#define PCLK_HPMCU_INTMUX 191
202+
#define CLK_HPMCU 192
203+
#define CLK_HPMCU_RTC 193
204+
#define DCLK_DECOM 194
205+
#define ACLK_DECOM 195
206+
#define PCLK_DECOM 196
207+
#define ACLK_SYS_SRAM 197
208+
#define PCLK_DMA2DDR 198
209+
#define ACLK_DMA2DDR 199
210+
#define PCLK_DCF 200
211+
#define ACLK_DCF 201
212+
#define MCLK_ACODEC_TX 202
213+
#define SCLK_UART0_SRC 203
214+
#define SCLK_UART1_SRC 204
215+
#define SCLK_UART2_SRC 205
216+
#define XIN_RC_SRC 206
217+
#define CLK_UTMI_USBOTG 207
218+
#define CLK_REF_USBPHY 208
219+
220+
#endif // _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H

0 commit comments

Comments
 (0)