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100 | 100 | #define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025 |
101 | 101 | #define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026 |
102 | 102 |
|
| 103 | +#define PCI_VENDOR_ID_SYSTEMBASE 0x14a1 |
| 104 | + |
103 | 105 | /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ |
104 | 106 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 |
105 | 107 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 |
@@ -2133,6 +2135,35 @@ pci_moxa_setup(struct serial_private *priv, |
2133 | 2135 | return setup_port(priv, port, bar, offset, 0); |
2134 | 2136 | } |
2135 | 2137 |
|
| 2138 | +#define SB_OPTR_IMR0 0x0c /* Interrupt mask register, p0 to p7 */ |
| 2139 | +static int pci_systembase_init(struct pci_dev *dev) |
| 2140 | +{ |
| 2141 | + resource_size_t iobase; |
| 2142 | + |
| 2143 | + if (!IS_ENABLED(CONFIG_HAS_IOPORT)) |
| 2144 | + return serial_8250_warn_need_ioport(dev); |
| 2145 | + |
| 2146 | + iobase = pci_resource_start(dev, 1); |
| 2147 | + |
| 2148 | + /* This will support up to 8 ports */ |
| 2149 | + outb(0xff, iobase + SB_OPTR_IMR0); |
| 2150 | + |
| 2151 | + return 0; |
| 2152 | +} |
| 2153 | + |
| 2154 | +static void pci_systembase_exit(struct pci_dev *dev) |
| 2155 | +{ |
| 2156 | + resource_size_t iobase; |
| 2157 | + |
| 2158 | + if (!IS_ENABLED(CONFIG_HAS_IOPORT)) { |
| 2159 | + serial_8250_warn_need_ioport(dev); |
| 2160 | + return; |
| 2161 | + } |
| 2162 | + |
| 2163 | + iobase = pci_resource_start(dev, 0); |
| 2164 | + outb(0x00, iobase + SB_OPTR_IMR0); |
| 2165 | +} |
| 2166 | + |
2136 | 2167 | /* |
2137 | 2168 | * Master list of serial port init/setup/exit quirks. |
2138 | 2169 | * This does not describe the general nature of the port. |
@@ -2481,6 +2512,16 @@ static struct pci_serial_quirk pci_serial_quirks[] = { |
2481 | 2512 | .init = pci_siig_init, |
2482 | 2513 | .setup = pci_siig_setup, |
2483 | 2514 | }, |
| 2515 | + /* Systembase */ |
| 2516 | + { |
| 2517 | + .vendor = PCI_VENDOR_ID_SYSTEMBASE, |
| 2518 | + .device = 0x0008, |
| 2519 | + .subvendor = PCI_ANY_ID, |
| 2520 | + .subdevice = PCI_ANY_ID, |
| 2521 | + .init = pci_systembase_init, |
| 2522 | + .setup = pci_default_setup, |
| 2523 | + .exit = pci_systembase_exit, |
| 2524 | + }, |
2484 | 2525 | /* |
2485 | 2526 | * Titan cards |
2486 | 2527 | */ |
@@ -3054,6 +3095,7 @@ enum pci_board_num_t { |
3054 | 3095 | pbn_b0_1_921600, |
3055 | 3096 | pbn_b0_2_921600, |
3056 | 3097 | pbn_b0_4_921600, |
| 3098 | + pbn_b0_8_921600, |
3057 | 3099 |
|
3058 | 3100 | pbn_b0_2_1130000, |
3059 | 3101 |
|
@@ -3254,6 +3296,12 @@ static struct pciserial_board pci_boards[] = { |
3254 | 3296 | .base_baud = 921600, |
3255 | 3297 | .uart_offset = 8, |
3256 | 3298 | }, |
| 3299 | + [pbn_b0_8_921600] = { |
| 3300 | + .flags = FL_BASE0, |
| 3301 | + .num_ports = 8, |
| 3302 | + .base_baud = 921600, |
| 3303 | + .uart_offset = 8, |
| 3304 | + }, |
3257 | 3305 |
|
3258 | 3306 | [pbn_b0_2_1130000] = { |
3259 | 3307 | .flags = FL_BASE0, |
@@ -6169,6 +6217,9 @@ static const struct pci_device_id serial_pci_tbl[] = { |
6169 | 6217 | PCI_ANY_ID, PCI_ANY_ID, |
6170 | 6218 | 0, 0, pbn_b0_1_115200 }, |
6171 | 6219 |
|
| 6220 | + /* Systembase Multi I/O cards */ |
| 6221 | + { PCI_VDEVICE(SYSTEMBASE, 0x0008), pbn_b0_8_921600 }, |
| 6222 | + |
6172 | 6223 | /* Fintek PCI serial cards */ |
6173 | 6224 | { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, |
6174 | 6225 | { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, |
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