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Pierre-Henry MoussayConchuOD
Pierre-Henry Moussay
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ConchuOD
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riscv: dts: microchip: add pic64gx and its curiosity kit
The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC prototyping board featuring a Microchip PIC64GX SoC PIC64GC-1000. Features include: - 1 GB DDR4 SDRAM - Gigabit Ethernet - microSD-card slot note: due to issue on some board, the SDHCI is limited to HS (High speed mode, with a clock of 50MHz and 3.3V signals). Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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‎arch/riscv/boot/dts/microchip/Makefile‎

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@@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP) += pic64gx-curiosity-kit.dtb

‎arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts‎

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Source for the PIC64GX Curiosity Kit
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*
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* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
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*
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* The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC
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* prototyping board featuring a Microchip PIC64GX SoC
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* PIC64GX-1000. Features include:
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* - 1 GB DDR4 SDRAM
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* - Gigabit Ethernet
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* - microSD-card slot
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*
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* https://www.microchip.com/en-us/development-tool/curiosity-pic64gx1000-kit-es
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*/
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/dts-v1/;
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#include "pic64gx.dtsi"
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#include "pic64gx-pinctrl.dtsi"
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/* Clock frequency (in Hz) of the rtcclk */
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#define RTCCLK_FREQ 1000000
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Microchip PIC64GX Curiosity Kit";
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compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx";
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aliases {
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ethernet0 = &mac0;
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serial1 = &mmuart1;
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serial2 = &mmuart2;
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};
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chosen {
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stdout-path = "serial1:115200n8";
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};
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cpus {
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timebase-frequency = <RTCCLK_FREQ>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hss: hss-buffer@bfc00000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0xbfc00000 0x0 0x400000>;
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no-map;
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};
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};
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};
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&gpio0 {
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interrupts = <13>, <14>, <15>, <16>,
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<17>, <18>, <19>, <20>,
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<21>, <22>, <23>, <24>,
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<25>, <26>;
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status ="okay";
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gpio-line-names =
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"", "", "", "", "", "", "", "",
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"", "", "", "", "MIPI_CAM_RESET", "MIPI_CAM_STANDBY";
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};
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&gpio1 {
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interrupts = <27>, <28>, <29>, <30>,
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<31>, <32>, <33>, <34>,
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<35>, <36>, <37>, <38>,
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<39>, <40>, <41>, <42>,
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<43>, <44>, <45>, <46>,
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<47>, <48>, <49>, <50>;
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status ="okay";
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gpio-line-names =
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"", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6",
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"LED7", "LED8", "", "", "", "", "", "",
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"", "", "", "", "HDMI_HPD", "", "", "GPIO_1_23";
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};
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&gpio2 {
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interrupts = <53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>;
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pinctrl-names = "default";
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pinctrl-0 = <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>,
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<&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>;
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status ="okay";
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gpio-line-names =
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"", "", "", "", "", "", "SWITCH2", "USR_IO12",
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"DIP1", "DIP2", "", "DIP3", "USR_IO1", "USR_IO2", "USR_IO7", "USR_IO8",
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"USR_IO3", "USR_IO4", "USR_IO5", "USR_IO6", "", "", "USR_IO9", "USR_IO10",
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"DIP4", "USR_IO11", "", "", "SWITCH1", "", "", "";
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};
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&mac0 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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pinctrl-names = "default";
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pinctrl-0 = <&mdio0_default>;
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phy0: ethernet-phy@b {
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reg = <0xb>;
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};
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};
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&mbox {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&mmc {
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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sdhci-caps-mask = <0x00000007 0x00000000>;
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status = "okay";
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};
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&mmuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_fio>;
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status = "okay";
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};
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&mmuart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_default>;
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status = "okay";
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&rtc {
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status = "okay";
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};
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&syscontroller {
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status = "okay";
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};

‎arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi‎

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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&iomux0 {
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spi0_fio: mux-spi0-fabric {
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function = "spi0";
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groups = "spi0_fabric";
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};
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spi1_mssio: mux-spi1-mssio {
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function = "spi1";
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groups = "spi1_mssio";
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};
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i2c0_mssio: mux-i2c0-mssio {
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function = "i2c0";
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groups = "i2c0_mssio";
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};
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i2c1_mssio: mux-i2c1-mssio {
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function = "i2c1";
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groups = "i2c1_mssio";
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};
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can0_fio: mux-can0-fabric {
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function = "can0";
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groups = "can0_fabric";
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};
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can1_fio: mux-can1-fabric {
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function = "can1";
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groups = "can1_fabric";
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};
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qspi_fio: mux-qspi-fabric {
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function = "qspi";
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groups = "qspi_fabric";
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};
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uart0_mssio: mux-uart0-mssio {
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function = "uart0";
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groups = "uart0_mssio";
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};
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uart1_fio: mux-uart1-fabric {
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function = "uart1";
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groups = "uart1_fabric";
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};
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uart2_fio: mux-uart2-fabric {
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function = "uart2";
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groups = "uart2_fabric";
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};
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uart3_fio: mux-uart3-fabric {
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function = "uart3";
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groups = "uart3_fabric";
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};
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uart4_fio: mux-uart4-fabric {
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function = "uart4";
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groups = "uart4_fabric";
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};
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mdio0_fio: mux-mdio0-fabric {
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function = "mdio0";
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groups = "mdio0_fabric";
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};
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mdio1_fio: mux-mdio1-fabric {
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function = "mdio1";
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groups = "mdio1_fabric";
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};
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};
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&gpio2_pinctrl {
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//TODO rethink the labels, since a bunch of these are not defaults or
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//just outright remove the non-default groups
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mdio0_default: mux-mac0 {
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function = "mdio0";
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groups = "mdio0";
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};
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mdio0_gpio: mux-mac0-gpio2 {
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function = "gpio";
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groups = "gpio_mdio0";
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};
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mdio1_default: mux-mac1 {
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function = "mdio1";
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groups = "mdio1";
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};
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mdio1_gpio: mux-mac1-gpio2 {
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function = "gpio";
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groups = "gpio_mdio1";
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};
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spi0_default: mux-spi0 {
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function = "spi0";
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groups = "spi0";
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};
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spi0_gpio: mux-spi0-gpio2 {
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function = "gpio";
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groups = "gpio_spi0";
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};
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can0_default: mux-can0 {
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function = "can0";
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groups = "can0";
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};
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can0_gpio: mux-can0-gpio2 {
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function = "gpio";
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groups = "gpio_can0";
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};
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pcie_default: mux-pcie {
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function = "pcie";
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groups = "pcie";
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};
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pcie_gpio: mux-pcie-gpio2 {
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function = "gpio";
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groups = "gpio_pcie";
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};
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qspi_default: mux-qspi {
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function = "qspi";
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groups = "qspi";
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};
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qspi_gpio: mux-qspi-gpio2 {
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function = "gpio";
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groups = "gpio_qspi";
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};
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uart3_default: mux-uart3 {
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function = "uart3";
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groups = "uart3";
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};
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uart3_gpio: mux-uart3-gpio2 {
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function = "gpio";
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groups = "gpio_uart3";
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};
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uart4_default: mux-uart4 {
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function = "uart4";
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groups = "uart4";
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};
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uart4_gpio: mux-uart4-gpio2 {
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function = "gpio";
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groups = "gpio_uart4";
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};
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can1_default: mux-can1 {
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function = "can1";
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groups = "can1";
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};
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can1_gpio: mux-can1-gpio2 {
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function = "gpio";
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groups = "gpio_can1";
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};
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uart2_default: mux-uart2 {
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function = "uart2";
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groups = "uart2";
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};
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uart2_gpio: mux-uart2-gpio2 {
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function = "gpio";
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groups = "gpio_uart2";
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};
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};

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