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André Svenssonbroonie
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regulator: da9121: Allow caching BUCK registers
Some BUCK registers may change without software writes when GPIO pins are configured for functions DVC/RELOAD/EN. If the board does not use these pin-controlled features, caching is possible. Caching BUCK registers removes unnecessary I2C reads when performing register updates. For example, updating regulator mode can result in two I2C reads, one from the regulator core regulator_set_mode() and one from the DA9121 driver, where da9121_buck_set_mode() uses regmap_update_bits() (read/modify/write). Check for the optional DT property dlg,no-gpio-control. When present, select the regmap configuration that does not mark the BUCK1 register block (DA9121_REG_BUCK_BUCK1_0..DA9121_REG_BUCK_BUCK1_6) as volatile, so that regmap can cache BUCK1 registers and avoid unnecessary I2C reads. The property dlg,no-gpio-control is required to ensure that BUCK1 registers can be cached, as the absence of relevant GPIO DT properties does not imply that the RELOAD/DVC/EN GPIO functions are unused. These functions are provided by DA91xx GPIO pins and may be controlled by external hardware without corresponding GPIO DT properties. The dlg,no-gpio-control property explicitly indicates that none of these GPIO functions are used. The dlg,no-gpio-control property is mutually exclusive with enable-gpios, regardless of whether the referenced GPIO is connected to a GPIO pin or the IC_EN pin, since pulling IC_EN low powers down the regulator and registers are reinitialized at startup, leaving cached values stale. Co-developed-by: Waqar Hameed <waqar.hameed@axis.com> Signed-off-by: Waqar Hameed <waqar.hameed@axis.com> Signed-off-by: André Svensson <andre.svensson@axis.com> Link: https://patch.msgid.link/20260320-no-gpio-control-v2-2-dbc938e462cb@axis.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Lines changed: 36 additions & 7 deletions

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drivers/regulator/da9121-regulator.c

Lines changed: 36 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -400,8 +400,14 @@ static int da9121_of_parse_cb(struct device_node *np,
400400
GPIOD_OUT_HIGH |
401401
GPIOD_FLAGS_BIT_NONEXCLUSIVE,
402402
"da9121-enable");
403-
if (!IS_ERR(ena_gpiod))
403+
if (!IS_ERR(ena_gpiod)) {
404+
if (of_property_read_bool(chip->dev->of_node, "dlg,no-gpio-control")) {
405+
gpiod_put(ena_gpiod);
406+
dev_err(chip->dev, "dlg,no-gpio-control conflicts with enable-gpios\n");
407+
return -EINVAL;
408+
}
404409
config->ena_gpiod = ena_gpiod;
410+
}
405411

406412
if (variant_parameters[chip->variant_id].num_bucks == 2) {
407413
uint32_t ripple_cancel;
@@ -864,6 +870,21 @@ static const struct regmap_access_table da9121_volatile_table = {
864870
.n_yes_ranges = ARRAY_SIZE(da9121_volatile_ranges),
865871
};
866872

873+
/*
874+
* When GPIO functions DVC/RELOAD/EN are not used, the registers in the range
875+
* DA9121_REG_BUCK_BUCK1_0 to DA9121_REG_BUCK_BUCK1_6 need not be volatile
876+
* because register writes to these registers can only be performed via I2C.
877+
*/
878+
static const struct regmap_range da9121_volatile_ranges_no_gpio_ctrl[] = {
879+
regmap_reg_range(DA9121_REG_SYS_STATUS_0, DA9121_REG_SYS_EVENT_2),
880+
regmap_reg_range(DA9121_REG_SYS_GPIO0_0, DA9121_REG_SYS_GPIO2_1),
881+
};
882+
883+
static const struct regmap_access_table da9121_volatile_table_no_gpio_ctrl = {
884+
.yes_ranges = da9121_volatile_ranges_no_gpio_ctrl,
885+
.n_yes_ranges = ARRAY_SIZE(da9121_volatile_ranges_no_gpio_ctrl),
886+
};
887+
867888
/* DA9121 regmap config for 1 channel variants */
868889
static const struct regmap_config da9121_1ch_regmap_config = {
869890
.reg_bits = 8,
@@ -994,40 +1015,48 @@ static int da9121_assign_chip_model(struct i2c_client *i2c,
9941015
struct da9121 *chip)
9951016
{
9961017
const struct regmap_config *regmap;
1018+
struct regmap_config regmap_config_1ch = da9121_1ch_regmap_config;
1019+
struct regmap_config regmap_config_2ch = da9121_2ch_regmap_config;
1020+
9971021
int ret = 0;
9981022

9991023
chip->dev = &i2c->dev;
10001024

1025+
if (of_property_read_bool(i2c->dev.of_node, "dlg,no-gpio-control")) {
1026+
regmap_config_1ch.volatile_table = &da9121_volatile_table_no_gpio_ctrl;
1027+
regmap_config_2ch.volatile_table = &da9121_volatile_table_no_gpio_ctrl;
1028+
}
1029+
10011030
/* Use configured subtype to select the regulator descriptor index and
10021031
* register map, common to both consumer and automotive grade variants
10031032
*/
10041033
switch (chip->subvariant_id) {
10051034
case DA9121_SUBTYPE_DA9121:
10061035
case DA9121_SUBTYPE_DA9130:
10071036
chip->variant_id = DA9121_TYPE_DA9121_DA9130;
1008-
regmap = &da9121_1ch_regmap_config;
1037+
regmap = &regmap_config_1ch;
10091038
break;
10101039
case DA9121_SUBTYPE_DA9217:
10111040
chip->variant_id = DA9121_TYPE_DA9217;
1012-
regmap = &da9121_1ch_regmap_config;
1041+
regmap = &regmap_config_1ch;
10131042
break;
10141043
case DA9121_SUBTYPE_DA9122:
10151044
case DA9121_SUBTYPE_DA9131:
10161045
chip->variant_id = DA9121_TYPE_DA9122_DA9131;
1017-
regmap = &da9121_2ch_regmap_config;
1046+
regmap = &regmap_config_2ch;
10181047
break;
10191048
case DA9121_SUBTYPE_DA9220:
10201049
case DA9121_SUBTYPE_DA9132:
10211050
chip->variant_id = DA9121_TYPE_DA9220_DA9132;
1022-
regmap = &da9121_2ch_regmap_config;
1051+
regmap = &regmap_config_2ch;
10231052
break;
10241053
case DA9121_SUBTYPE_DA9141:
10251054
chip->variant_id = DA9121_TYPE_DA9141;
1026-
regmap = &da9121_1ch_regmap_config;
1055+
regmap = &regmap_config_1ch;
10271056
break;
10281057
case DA9121_SUBTYPE_DA9142:
10291058
chip->variant_id = DA9121_TYPE_DA9142;
1030-
regmap = &da9121_2ch_regmap_config;
1059+
regmap = &regmap_config_2ch;
10311060
break;
10321061
default:
10331062
return -EINVAL;

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