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Merge tag 'socfpga_updates_for_v7.1_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v7.1 - dt-bindings updates: - Document fallback compatible for Stratix10 SoCDK eMMC board - Document compatible for the Agilex5 SoCFPGA modular board - Add emmc support for the Stratix10 - Drop CPU masks from the GICv3 PPI interrupts for Agilex5 * tag 'socfpga_updates_for_v7.1_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts dt-bindings: intel: Add Agilex5 SoCFPGA modular board arm64: dts: socfpga: stratix10: Add emmc support dt-bindings: altera: Add fallback compatible for Stratix 10 SoCDK eMMC variant Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 9988201 + 625af11 commit 6935cce

6 files changed

Lines changed: 166 additions & 69 deletions

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‎Documentation/devicetree/bindings/arm/altera.yaml‎

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@@ -84,6 +84,12 @@ properties:
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- altr,socfpga-stratix10-swvp
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- const: altr,socfpga-stratix10
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- description: Stratix 10 SoCDK eMMC variant
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items:
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- const: altr,socfpga-stratix10-socdk-emmc
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- const: altr,socfpga-stratix10-socdk
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- const: altr,socfpga-stratix10
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- description: AgileX boards
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items:
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- enum:
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- enum:
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- intel,socfpga-agilex5-socdk
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- intel,socfpga-agilex5-socdk-013b
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- intel,socfpga-agilex5-socdk-modular
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- intel,socfpga-agilex5-socdk-nand
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- const: intel,socfpga-agilex5
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‎arch/arm64/boot/dts/altera/Makefile‎

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# SPDX-License-Identifier: GPL-2.0-only
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dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \
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socfpga_stratix10_socdk_emmc.dtb \
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socfpga_stratix10_socdk_nand.dtb \
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socfpga_stratix10_swvp.dtb

‎arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts‎

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@@ -3,53 +3,11 @@
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* Copyright Altera Corporation (C) 2015. All rights reserved.
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*/
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6-
#include "socfpga_stratix10.dtsi"
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#include "socfpga_stratix10_socdk.dtsi"
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/ {
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model = "SoCFPGA Stratix 10 SoCDK";
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compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
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aliases {
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serial0 = &uart0;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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ethernet2 = &gmac2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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led-hps0 {
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label = "hps_led0";
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gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
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};
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led-hps1 {
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label = "hps_led1";
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gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
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};
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led-hps2 {
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label = "hps_led2";
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gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0x80000000 0 0>;
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};
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ref_033v: regulator-v-ref {
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compatible = "regulator-fixed";
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regulator-name = "0.33V";
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regulator-min-microvolt = <330000>;
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regulator-max-microvolt = <330000>;
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};
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};
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&pinctrl0 {
@@ -68,10 +26,6 @@
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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phy0: ethernet-phy@4 {
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reg = <4>;
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txd0-skew-ps = <0>; /* -420ps */
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clk-phase-sd-hs = <0>, <135>;
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};
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&osc1 {
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clock-frequency = <25000000>;
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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disable-over-current;
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};
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&watchdog0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <100000>;

‎arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtsi‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright Altera Corporation (C) 2026. All rights reserved.
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*/
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#include "socfpga_stratix10.dtsi"
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/ {
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aliases {
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serial0 = &uart0;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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ethernet2 = &gmac2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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led-hps0 {
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label = "hps_led0";
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gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
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};
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led-hps1 {
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label = "hps_led1";
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gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
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};
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led-hps2 {
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label = "hps_led2";
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gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0x80000000 0 0>;
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};
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ref_033v: regulator-0v33-ref {
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compatible = "regulator-fixed";
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regulator-name = "0.33V";
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regulator-min-microvolt = <330000>;
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regulator-max-microvolt = <330000>;
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};
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};
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&gpio1 {
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status = "okay";
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};
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&osc1 {
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clock-frequency = <25000000>;
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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disable-over-current;
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};
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&watchdog0 {
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status = "okay";
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};

‎arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_emmc.dts‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright Altera Corporation (C) 2026. All rights reserved.
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*/
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6+
#include "socfpga_stratix10_socdk.dtsi"
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8+
/ {
9+
model = "SoCFPGA Stratix 10 SoCDK eMMC daughter board";
10+
compatible = "altr,socfpga-stratix10-socdk-emmc",
11+
"altr,socfpga-stratix10-socdk",
12+
"altr,socfpga-stratix10";
13+
};
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&gmac2 {
16+
status = "okay";
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/* PHY delays is configured via skew properties */
18+
phy-mode = "rgmii";
19+
phy-handle = <&phy0>;
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21+
max-frame-size = <9000>;
22+
23+
mdio0 {
24+
#address-cells = <1>;
25+
#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
27+
phy0: ethernet-phy@4 {
28+
reg = <4>;
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30+
txd0-skew-ps = <0>; /* -420ps */
31+
txd1-skew-ps = <0>; /* -420ps */
32+
txd2-skew-ps = <0>; /* -420ps */
33+
txd3-skew-ps = <0>; /* -420ps */
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rxd0-skew-ps = <420>; /* 0ps */
35+
rxd1-skew-ps = <420>; /* 0ps */
36+
rxd2-skew-ps = <420>; /* 0ps */
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rxd3-skew-ps = <420>; /* 0ps */
38+
txen-skew-ps = <0>; /* -420ps */
39+
txc-skew-ps = <900>; /* 0ps */
40+
rxdv-skew-ps = <420>; /* 0ps */
41+
rxc-skew-ps = <1680>; /* 780ps */
42+
};
43+
};
44+
};
45+
46+
&mmc {
47+
status = "okay";
48+
cap-mmc-highspeed;
49+
broken-cd;
50+
bus-width = <4>;
51+
clk-phase-sd-hs = <0>, <135>;
52+
};
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54+
&i2c2 {
55+
status = "okay";
56+
clock-frequency = <100000>;
57+
i2c-sda-falling-time-ns = <890>; /* hcnt */
58+
i2c-scl-falling-time-ns = <890>; /* lcnt */
59+
60+
adc@14 {
61+
compatible = "lltc,ltc2497";
62+
reg = <0x14>;
63+
vref-supply = <&ref_033v>;
64+
};
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66+
temp@4c {
67+
compatible = "maxim,max1619";
68+
reg = <0x4c>;
69+
};
70+
71+
eeprom@51 {
72+
compatible = "atmel,24c32";
73+
reg = <0x51>;
74+
pagesize = <32>;
75+
};
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77+
rtc@68 {
78+
compatible = "dallas,ds1339";
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reg = <0x68>;
80+
};
81+
};

‎arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi‎

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152152
timer {
153153
compatible = "arm,armv8-timer";
154154
interrupt-parent = <&intc>;
155-
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
156-
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
157-
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
158-
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
155+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
156+
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
157+
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
158+
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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usbphy0: usbphy {

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