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aluceropdavejiang
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cxl: Move pci generic code from cxl_pci to core/cxl_pci
Inside cxl/core/pci.c there are helpers for CXL PCIe initialization meanwhile cxl/pci_drv.c implements the functionality for a Type3 device initialization. In preparation for type2 support, move helper functions from cxl/pci.c to cxl/core/pci.c in order to be exported and used by type2 drivers. [ dj: Clarified subject. ] Signed-off-by: Alejandro Lucero <alucerop@amd.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20260306164741.3796372-4-alejandro.lucero-palau@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
1 parent 0058698 commit 58f2893

6 files changed

Lines changed: 77 additions & 73 deletions

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drivers/cxl/core/core.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -224,4 +224,6 @@ int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid,
224224
u16 *return_code);
225225
#endif
226226

227+
resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
228+
struct cxl_dport *dport);
227229
#endif /* __CXL_CORE_H__ */

drivers/cxl/core/pci.c

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -696,6 +696,68 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port)
696696
}
697697
EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, "CXL");
698698

699+
static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
700+
struct cxl_register_map *map,
701+
struct cxl_dport *dport)
702+
{
703+
resource_size_t component_reg_phys;
704+
705+
*map = (struct cxl_register_map) {
706+
.host = &pdev->dev,
707+
.resource = CXL_RESOURCE_NONE,
708+
};
709+
710+
struct cxl_port *port __free(put_cxl_port) =
711+
cxl_pci_find_port(pdev, &dport);
712+
if (!port)
713+
return -EPROBE_DEFER;
714+
715+
component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport);
716+
if (component_reg_phys == CXL_RESOURCE_NONE)
717+
return -ENXIO;
718+
719+
map->resource = component_reg_phys;
720+
map->reg_type = CXL_REGLOC_RBI_COMPONENT;
721+
map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
722+
723+
return 0;
724+
}
725+
726+
int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
727+
struct cxl_register_map *map)
728+
{
729+
int rc;
730+
731+
rc = cxl_find_regblock(pdev, type, map);
732+
733+
/*
734+
* If the Register Locator DVSEC does not exist, check if it
735+
* is an RCH and try to extract the Component Registers from
736+
* an RCRB.
737+
*/
738+
if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) {
739+
struct cxl_dport *dport;
740+
struct cxl_port *port __free(put_cxl_port) =
741+
cxl_pci_find_port(pdev, &dport);
742+
if (!port)
743+
return -EPROBE_DEFER;
744+
745+
rc = cxl_rcrb_get_comp_regs(pdev, map, dport);
746+
if (rc)
747+
return rc;
748+
749+
rc = cxl_dport_map_rcd_linkcap(pdev, dport);
750+
if (rc)
751+
return rc;
752+
753+
} else if (rc) {
754+
return rc;
755+
}
756+
757+
return cxl_setup_regs(map);
758+
}
759+
EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL");
760+
699761
int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c)
700762
{
701763
int speed, bw;

drivers/cxl/core/regs.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -641,4 +641,3 @@ resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
641641
return CXL_RESOURCE_NONE;
642642
return __rcrb_to_component(dev, &dport->rcrb, CXL_RCRB_UPSTREAM);
643643
}
644-
EXPORT_SYMBOL_NS_GPL(cxl_rcd_component_reg_phys, "CXL");

drivers/cxl/cxl.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -222,8 +222,6 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
222222
struct cxl_register_map *map);
223223
int cxl_setup_regs(struct cxl_register_map *map);
224224
struct cxl_dport;
225-
resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
226-
struct cxl_dport *dport);
227225
int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport);
228226

229227
#define CXL_RESOURCE_NONE ((resource_size_t) -1)

drivers/cxl/cxlpci.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,17 @@ static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
7474
return lnksta2 & PCI_EXP_LNKSTA2_FLIT;
7575
}
7676

77+
/*
78+
* Assume that the caller has already validated that @pdev has CXL
79+
* capabilities, any RCiEP with CXL capabilities is treated as a
80+
* Restricted CXL Device (RCD) and finds upstream port and endpoint
81+
* registers in a Root Complex Register Block (RCRB).
82+
*/
83+
static inline bool is_cxl_restricted(struct pci_dev *pdev)
84+
{
85+
return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END;
86+
}
87+
7788
struct cxl_dev_state;
7889
void read_cdat_data(struct cxl_port *port);
7990

@@ -101,4 +112,6 @@ static inline void devm_cxl_port_ras_setup(struct cxl_port *port)
101112
}
102113
#endif
103114

115+
int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
116+
struct cxl_register_map *map);
104117
#endif /* __CXL_PCI_H__ */

drivers/cxl/pci.c

Lines changed: 0 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -465,76 +465,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail)
465465
return 0;
466466
}
467467

468-
/*
469-
* Assume that any RCIEP that emits the CXL memory expander class code
470-
* is an RCD
471-
*/
472-
static bool is_cxl_restricted(struct pci_dev *pdev)
473-
{
474-
return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END;
475-
}
476-
477-
static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
478-
struct cxl_register_map *map,
479-
struct cxl_dport *dport)
480-
{
481-
resource_size_t component_reg_phys;
482-
483-
*map = (struct cxl_register_map) {
484-
.host = &pdev->dev,
485-
.resource = CXL_RESOURCE_NONE,
486-
};
487-
488-
struct cxl_port *port __free(put_cxl_port) =
489-
cxl_pci_find_port(pdev, &dport);
490-
if (!port)
491-
return -EPROBE_DEFER;
492-
493-
component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport);
494-
if (component_reg_phys == CXL_RESOURCE_NONE)
495-
return -ENXIO;
496-
497-
map->resource = component_reg_phys;
498-
map->reg_type = CXL_REGLOC_RBI_COMPONENT;
499-
map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
500-
501-
return 0;
502-
}
503-
504-
static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
505-
struct cxl_register_map *map)
506-
{
507-
int rc;
508-
509-
rc = cxl_find_regblock(pdev, type, map);
510-
511-
/*
512-
* If the Register Locator DVSEC does not exist, check if it
513-
* is an RCH and try to extract the Component Registers from
514-
* an RCRB.
515-
*/
516-
if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) {
517-
struct cxl_dport *dport;
518-
struct cxl_port *port __free(put_cxl_port) =
519-
cxl_pci_find_port(pdev, &dport);
520-
if (!port)
521-
return -EPROBE_DEFER;
522-
523-
rc = cxl_rcrb_get_comp_regs(pdev, map, dport);
524-
if (rc)
525-
return rc;
526-
527-
rc = cxl_dport_map_rcd_linkcap(pdev, dport);
528-
if (rc)
529-
return rc;
530-
531-
} else if (rc) {
532-
return rc;
533-
}
534-
535-
return cxl_setup_regs(map);
536-
}
537-
538468
static void free_event_buf(void *buf)
539469
{
540470
kvfree(buf);

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