@@ -737,10 +737,6 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
737737 unsigned long rate , unsigned long * prate ,
738738 const struct clk_div_table * table ,
739739 u8 width , unsigned long flags );
740- long divider_ro_round_rate_parent (struct clk_hw * hw , struct clk_hw * parent ,
741- unsigned long rate , unsigned long * prate ,
742- const struct clk_div_table * table , u8 width ,
743- unsigned long flags , unsigned int val );
744740int divider_determine_rate (struct clk_hw * hw , struct clk_rate_request * req ,
745741 const struct clk_div_table * table , u8 width ,
746742 unsigned long flags );
@@ -1440,17 +1436,6 @@ static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
14401436 rate , prate , table , width , flags );
14411437}
14421438
1443- static inline long divider_ro_round_rate (struct clk_hw * hw , unsigned long rate ,
1444- unsigned long * prate ,
1445- const struct clk_div_table * table ,
1446- u8 width , unsigned long flags ,
1447- unsigned int val )
1448- {
1449- return divider_ro_round_rate_parent (hw , clk_hw_get_parent (hw ),
1450- rate , prate , table , width , flags ,
1451- val );
1452- }
1453-
14541439/*
14551440 * FIXME clock api without lock protection
14561441 */
0 commit comments