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Merge tag 'phy-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul: "New Support: - Qualcomm Eliza QMP UFS PHY - Canaan K230 USB 2.0 PHY driver - Mediatek mt8167 dsi-phy - Eswin EIC7700 SATA PHY driver Updates: - Sorted subsytem Makefile/Kconfig and some kernel-doc udpates" * tag 'phy-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Eliza QMP UFS PHY phy: qcom: m31-eusb2: clear PLL_EN during init phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY phy: apple: apple: Use local variable for ioremap return value phy: qcom: qmp-usbc: Simplify check for non-NULL pointer phy: marvell: mmp3-hsic: Avoid re-casting __iomem phy: apple: atc: Make atcphy_dwc3_reset_ops variable static dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167 phy: usb: Add driver for Canaan K230 USB 2.0 PHY dt-bindings: phy: Add Canaan K230 USB PHY phy: phy-mtk-tphy: Update names and format of kernel-doc comments phy: Sort the subsystem Kconfig phy: Sort the subsystem Makefile phy: move spacemit pcie driver to its subfolder
2 parents 65bec0c + caf0851 commit 3f887ed

19 files changed

Lines changed: 816 additions & 81 deletions

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‎Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/phy/canaan,k230-usb-phy.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
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title: Canaan K230 USB2.0 PHY
8+
9+
maintainers:
10+
- Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
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properties:
13+
compatible:
14+
const: canaan,k230-usb-phy
15+
16+
reg:
17+
maxItems: 1
18+
19+
"#phy-cells":
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const: 1
21+
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required:
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- compatible
24+
- reg
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- "#phy-cells"
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27+
additionalProperties: false
28+
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examples:
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- |
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usbphy: usb-phy@91585000 {
32+
compatible = "canaan,k230-usb-phy";
33+
reg = <0x91585000 0x400>;
34+
#phy-cells = <1>;
35+
};

‎Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Eswin EIC7700 SoC SATA PHY
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maintainers:
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- Yulin Lu <luyulin@eswincomputing.com>
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- Huan He <hehuan1@eswincomputing.com>
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properties:
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compatible:
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const: eswin,eic7700-sata-phy
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: phy
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: port
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- const: phy
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eswin,tx-amplitude-tuning:
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description: This adjusts the transmitter amplitude signal, and its value
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is derived from eye diagram tuning. The three values correspond to Gen1,
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Gen2, and Gen3 parameters respectively.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: Gen1 parameter.
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minimum: 0
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maximum: 0x7f
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- description: Gen2 parameter.
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minimum: 0
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maximum: 0x7f
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- description: Gen3 parameter.
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minimum: 0
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maximum: 0x7f
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default: [0, 0, 0]
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eswin,tx-preemph-tuning:
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description: This adjusts the transmitter de-emphasis signal, and its value
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is derived from eye diagram tuning. The three values correspond to Gen1,
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Gen2, and Gen3 parameters respectively.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: Gen1 parameter.
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minimum: 0
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maximum: 0x3f
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- description: Gen2 parameter.
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minimum: 0
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maximum: 0x3f
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- description: Gen3 parameter.
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minimum: 0
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maximum: 0x3f
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default: [0, 0, 0]
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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sata-phy@50440300 {
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compatible = "eswin,eic7700-sata-phy";
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reg = <0x50440300 0x40>;
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clocks = <&hspcrg 17>;
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clock-names = "phy";
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resets = <&hspcrg 0>, <&hspcrg 1>;
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reset-names = "port", "phy";
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#phy-cells = <0>;
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};

‎Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,10 @@ description:
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,qcs8300-qmp-ufs-phy
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- const: qcom,sa8775p-qmp-ufs-phy
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- items:
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- enum:
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- qcom,qcs615-qmp-ufs-phy
@@ -26,8 +30,8 @@ properties:
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- const: qcom,sm8550-qmp-ufs-phy
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- items:
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- enum:
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- qcom,qcs8300-qmp-ufs-phy
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- const: qcom,sa8775p-qmp-ufs-phy
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- qcom,eliza-qmp-ufs-phy
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- const: qcom,sm8650-qmp-ufs-phy
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- items:
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- enum:
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- qcom,kaanapali-qmp-ufs-phy

‎drivers/phy/Kconfig‎

Lines changed: 46 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,26 @@ config GENERIC_PHY_MIPI_DPHY
4646
Provides a number of helpers a core functions for MIPI D-PHY
4747
drivers to us.
4848

49+
config PHY_AIROHA_PCIE
50+
tristate "Airoha PCIe-PHY Driver"
51+
depends on ARCH_AIROHA || COMPILE_TEST
52+
depends on OF
53+
select GENERIC_PHY
54+
help
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Say Y here to add support for Airoha PCIe PHY driver.
56+
This driver create the basic PHY instance and provides initialize
57+
callback for PCIe GEN3 port.
58+
59+
config PHY_CAN_TRANSCEIVER
60+
tristate "CAN transceiver PHY"
61+
select GENERIC_PHY
62+
select MULTIPLEXER
63+
help
64+
This option enables support for CAN transceivers as a PHY. This
65+
driver provides function for putting the transceivers in various
66+
functional modes using gpios and sets the attribute max link
67+
rate, for CAN drivers.
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4969
config PHY_GOOGLE_USB
5070
tristate "Google Tensor SoC USB PHY driver"
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select GENERIC_PHY
@@ -57,6 +77,18 @@ config PHY_GOOGLE_USB
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both of which are integrated with the DWC3 USB DRD controller.
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This driver currently supports USB high-speed.
5979

80+
config USB_LGM_PHY
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tristate "INTEL Lightning Mountain USB PHY Driver"
82+
depends on USB_SUPPORT
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depends on X86 || COMPILE_TEST
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select USB_PHY
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select REGULATOR
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select REGULATOR_FIXED_VOLTAGE
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help
88+
Enable this to support Intel DWC3 PHY USB phy. This driver provides
89+
interface to interact with USB GEN-II and USB 3.x PHY that is part
90+
of the Intel network SOC.
91+
6092
config PHY_LPC18XX_USB_OTG
6193
tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
6294
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
@@ -68,6 +100,17 @@ config PHY_LPC18XX_USB_OTG
68100
This driver is need for USB0 support on LPC18xx/43xx and takes
69101
care of enabling and clock setup.
70102

103+
config PHY_NXP_PTN3222
104+
tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"
105+
depends on I2C
106+
depends on OF
107+
select GENERIC_PHY
108+
help
109+
Enable this to support NXP PTN3222 1-port eUSB2 to USB2 Redriver.
110+
This redriver performs translation between eUSB2 and USB2 signalling
111+
schemes. It supports all three USB 2.0 data rates: Low Speed, Full
112+
Speed and High Speed.
113+
71114
config PHY_PISTACHIO_USB
72115
tristate "IMG Pistachio USB2.0 PHY driver"
73116
depends on MIPS || COMPILE_TEST
@@ -90,69 +133,17 @@ config PHY_XGENE
90133
help
91134
This option enables support for APM X-Gene SoC multi-purpose PHY.
92135

93-
config USB_LGM_PHY
94-
tristate "INTEL Lightning Mountain USB PHY Driver"
95-
depends on USB_SUPPORT
96-
depends on X86 || COMPILE_TEST
97-
select USB_PHY
98-
select REGULATOR
99-
select REGULATOR_FIXED_VOLTAGE
100-
help
101-
Enable this to support Intel DWC3 PHY USB phy. This driver provides
102-
interface to interact with USB GEN-II and USB 3.x PHY that is part
103-
of the Intel network SOC.
104-
105-
config PHY_CAN_TRANSCEIVER
106-
tristate "CAN transceiver PHY"
107-
select GENERIC_PHY
108-
select MULTIPLEXER
109-
help
110-
This option enables support for CAN transceivers as a PHY. This
111-
driver provides function for putting the transceivers in various
112-
functional modes using gpios and sets the attribute max link
113-
rate, for CAN drivers.
114-
115-
config PHY_AIROHA_PCIE
116-
tristate "Airoha PCIe-PHY Driver"
117-
depends on ARCH_AIROHA || COMPILE_TEST
118-
depends on OF
119-
select GENERIC_PHY
120-
help
121-
Say Y here to add support for Airoha PCIe PHY driver.
122-
This driver create the basic PHY instance and provides initialize
123-
callback for PCIe GEN3 port.
124-
125-
config PHY_NXP_PTN3222
126-
tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"
127-
depends on I2C
128-
depends on OF
129-
select GENERIC_PHY
130-
help
131-
Enable this to support NXP PTN3222 1-port eUSB2 to USB2 Redriver.
132-
This redriver performs translation between eUSB2 and USB2 signalling
133-
schemes. It supports all three USB 2.0 data rates: Low Speed, Full
134-
Speed and High Speed.
135-
136-
config PHY_SPACEMIT_K1_PCIE
137-
tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"
138-
depends on ARCH_SPACEMIT || COMPILE_TEST
139-
depends on COMMON_CLK
140-
depends on HAS_IOMEM
141-
depends on OF
142-
select GENERIC_PHY
143-
default ARCH_SPACEMIT
144-
help
145-
Enable support for the PCIe and USB 3 combo PHY and two
146-
PCIe-only PHYs used in the SpacemiT K1 SoC.
147-
148136
source "drivers/phy/allwinner/Kconfig"
149137
source "drivers/phy/amlogic/Kconfig"
150138
source "drivers/phy/apple/Kconfig"
151139
source "drivers/phy/broadcom/Kconfig"
152140
source "drivers/phy/cadence/Kconfig"
141+
source "drivers/phy/canaan/Kconfig"
142+
source "drivers/phy/eswin/Kconfig"
153143
source "drivers/phy/freescale/Kconfig"
154144
source "drivers/phy/hisilicon/Kconfig"
155145
source "drivers/phy/ingenic/Kconfig"
146+
source "drivers/phy/intel/Kconfig"
156147
source "drivers/phy/lantiq/Kconfig"
157148
source "drivers/phy/marvell/Kconfig"
158149
source "drivers/phy/mediatek/Kconfig"
@@ -174,7 +165,6 @@ source "drivers/phy/starfive/Kconfig"
174165
source "drivers/phy/sunplus/Kconfig"
175166
source "drivers/phy/tegra/Kconfig"
176167
source "drivers/phy/ti/Kconfig"
177-
source "drivers/phy/intel/Kconfig"
178168
source "drivers/phy/xilinx/Kconfig"
179169

180170
endmenu

‎drivers/phy/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -7,21 +7,23 @@ obj-$(CONFIG_PHY_COMMON_PROPS) += phy-common-props.o
77
obj-$(CONFIG_PHY_COMMON_PROPS_TEST) += phy-common-props-test.o
88
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
99
obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
10+
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
1011
obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
1112
obj-$(CONFIG_PHY_GOOGLE_USB) += phy-google-usb.o
13+
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
1214
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
13-
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
15+
obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
1416
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
1517
obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
16-
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
17-
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
18-
obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
19-
obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o
18+
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
19+
2020
obj-$(CONFIG_GENERIC_PHY) += allwinner/ \
2121
amlogic/ \
2222
apple/ \
2323
broadcom/ \
2424
cadence/ \
25+
canaan/ \
26+
eswin/ \
2527
freescale/ \
2628
hisilicon/ \
2729
ingenic/ \

‎drivers/phy/apple/atc.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2023,7 +2023,7 @@ static int atcphy_dwc3_reset_deassert(struct reset_controller_dev *rcdev, unsign
20232023
return 0;
20242024
}
20252025

2026-
const struct reset_control_ops atcphy_dwc3_reset_ops = {
2026+
static const struct reset_control_ops atcphy_dwc3_reset_ops = {
20272027
.assert = atcphy_dwc3_reset_assert,
20282028
.deassert = atcphy_dwc3_reset_deassert,
20292029
};
@@ -2202,14 +2202,16 @@ static int atcphy_map_resources(struct platform_device *pdev, struct apple_atcph
22022202
{ "pipehandler", &atcphy->regs.pipehandler, NULL },
22032203
};
22042204
struct resource *res;
2205+
void __iomem *addr;
22052206

22062207
for (int i = 0; i < ARRAY_SIZE(resources); i++) {
22072208
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resources[i].name);
2208-
*resources[i].addr = devm_ioremap_resource(&pdev->dev, res);
2209-
if (IS_ERR(resources[i].addr))
2210-
return dev_err_probe(atcphy->dev, PTR_ERR(resources[i].addr),
2209+
addr = devm_ioremap_resource(&pdev->dev, res);
2210+
if (IS_ERR(addr))
2211+
return dev_err_probe(atcphy->dev, PTR_ERR(addr),
22112212
"Unable to map %s regs", resources[i].name);
22122213

2214+
*resources[i].addr = addr;
22132215
if (resources[i].res)
22142216
*resources[i].res = res;
22152217
}

‎drivers/phy/canaan/Kconfig‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
# SPDX-License-Identifier: GPL-2.0-only
2+
#
3+
# Phy drivers for Canaan platforms
4+
#
5+
config PHY_CANAAN_USB
6+
tristate "Canaan USB2 PHY Driver"
7+
depends on (ARCH_CANAAN || COMPILE_TEST) && OF
8+
select GENERIC_PHY
9+
help
10+
Enable this driver to support the USB 2.0 PHY controller
11+
on Canaan K230 RISC-V SoCs. This PHY controller
12+
provides physical layer functionality for USB 2.0 devices.
13+
If you have a Canaan K230 board and need USB 2.0 support,
14+
say Y or M here.

‎drivers/phy/canaan/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
obj-$(CONFIG_PHY_CANAAN_USB) += phy-k230-usb.o

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