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gregkhgregkh
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Merge tag 'counter-fixes-for-7.0' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-linus
William writes: Counter fixes for 7.0 Two fixes for rz-mut3-cnt: synchronize runtime PM usage count to toggle state of the counter, and set counter->parent during probe to ensure the current dev pointer is accessed during driver operation. * tag 'counter-fixes-for-7.0' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wbg/counter: counter: rz-mtu3-cnt: do not use struct rz_mtu3_channel's dev member counter: rz-mtu3-cnt: prevent counter from being toggled multiple times
2 parents f40b140 + 2932095 commit 3e68690

1 file changed

Lines changed: 35 additions & 32 deletions

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‎drivers/counter/rz-mtu3-cnt.c‎

Lines changed: 35 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -107,9 +107,9 @@ static bool rz_mtu3_is_counter_invalid(struct counter_device *counter, int id)
107107
struct rz_mtu3_cnt *const priv = counter_priv(counter);
108108
unsigned long tmdr;
109109

110-
pm_runtime_get_sync(priv->ch->dev);
110+
pm_runtime_get_sync(counter->parent);
111111
tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
112-
pm_runtime_put(priv->ch->dev);
112+
pm_runtime_put(counter->parent);
113113

114114
if (id == RZ_MTU3_32_BIT_CH && test_bit(RZ_MTU3_TMDR3_LWA, &tmdr))
115115
return false;
@@ -165,12 +165,12 @@ static int rz_mtu3_count_read(struct counter_device *counter,
165165
if (ret)
166166
return ret;
167167

168-
pm_runtime_get_sync(ch->dev);
168+
pm_runtime_get_sync(counter->parent);
169169
if (count->id == RZ_MTU3_32_BIT_CH)
170170
*val = rz_mtu3_32bit_ch_read(ch, RZ_MTU3_TCNTLW);
171171
else
172172
*val = rz_mtu3_16bit_ch_read(ch, RZ_MTU3_TCNT);
173-
pm_runtime_put(ch->dev);
173+
pm_runtime_put(counter->parent);
174174
mutex_unlock(&priv->lock);
175175

176176
return 0;
@@ -187,26 +187,26 @@ static int rz_mtu3_count_write(struct counter_device *counter,
187187
if (ret)
188188
return ret;
189189

190-
pm_runtime_get_sync(ch->dev);
190+
pm_runtime_get_sync(counter->parent);
191191
if (count->id == RZ_MTU3_32_BIT_CH)
192192
rz_mtu3_32bit_ch_write(ch, RZ_MTU3_TCNTLW, val);
193193
else
194194
rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TCNT, val);
195-
pm_runtime_put(ch->dev);
195+
pm_runtime_put(counter->parent);
196196
mutex_unlock(&priv->lock);
197197

198198
return 0;
199199
}
200200

201201
static int rz_mtu3_count_function_read_helper(struct rz_mtu3_channel *const ch,
202-
struct rz_mtu3_cnt *const priv,
202+
struct counter_device *const counter,
203203
enum counter_function *function)
204204
{
205205
u8 timer_mode;
206206

207-
pm_runtime_get_sync(ch->dev);
207+
pm_runtime_get_sync(counter->parent);
208208
timer_mode = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TMDR1);
209-
pm_runtime_put(ch->dev);
209+
pm_runtime_put(counter->parent);
210210

211211
switch (timer_mode & RZ_MTU3_TMDR1_PH_CNT_MODE_MASK) {
212212
case RZ_MTU3_TMDR1_PH_CNT_MODE_1:
@@ -240,7 +240,7 @@ static int rz_mtu3_count_function_read(struct counter_device *counter,
240240
if (ret)
241241
return ret;
242242

243-
ret = rz_mtu3_count_function_read_helper(ch, priv, function);
243+
ret = rz_mtu3_count_function_read_helper(ch, counter, function);
244244
mutex_unlock(&priv->lock);
245245

246246
return ret;
@@ -279,9 +279,9 @@ static int rz_mtu3_count_function_write(struct counter_device *counter,
279279
return -EINVAL;
280280
}
281281

282-
pm_runtime_get_sync(ch->dev);
282+
pm_runtime_get_sync(counter->parent);
283283
rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TMDR1, timer_mode);
284-
pm_runtime_put(ch->dev);
284+
pm_runtime_put(counter->parent);
285285
mutex_unlock(&priv->lock);
286286

287287
return 0;
@@ -300,9 +300,9 @@ static int rz_mtu3_count_direction_read(struct counter_device *counter,
300300
if (ret)
301301
return ret;
302302

303-
pm_runtime_get_sync(ch->dev);
303+
pm_runtime_get_sync(counter->parent);
304304
tsr = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TSR);
305-
pm_runtime_put(ch->dev);
305+
pm_runtime_put(counter->parent);
306306

307307
*direction = (tsr & RZ_MTU3_TSR_TCFD) ?
308308
COUNTER_COUNT_DIRECTION_FORWARD : COUNTER_COUNT_DIRECTION_BACKWARD;
@@ -377,14 +377,14 @@ static int rz_mtu3_count_ceiling_write(struct counter_device *counter,
377377
return -EINVAL;
378378
}
379379

380-
pm_runtime_get_sync(ch->dev);
380+
pm_runtime_get_sync(counter->parent);
381381
if (count->id == RZ_MTU3_32_BIT_CH)
382382
rz_mtu3_32bit_ch_write(ch, RZ_MTU3_TGRALW, ceiling);
383383
else
384384
rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TGRA, ceiling);
385385

386386
rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TCR, RZ_MTU3_TCR_CCLR_TGRA);
387-
pm_runtime_put(ch->dev);
387+
pm_runtime_put(counter->parent);
388388
mutex_unlock(&priv->lock);
389389

390390
return 0;
@@ -495,25 +495,28 @@ static int rz_mtu3_count_enable_read(struct counter_device *counter,
495495
static int rz_mtu3_count_enable_write(struct counter_device *counter,
496496
struct counter_count *count, u8 enable)
497497
{
498-
struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
499498
struct rz_mtu3_cnt *const priv = counter_priv(counter);
500499
int ret = 0;
501500

501+
mutex_lock(&priv->lock);
502+
503+
if (priv->count_is_enabled[count->id] == enable)
504+
goto exit;
505+
502506
if (enable) {
503-
mutex_lock(&priv->lock);
504-
pm_runtime_get_sync(ch->dev);
507+
pm_runtime_get_sync(counter->parent);
505508
ret = rz_mtu3_initialize_counter(counter, count->id);
506509
if (ret == 0)
507510
priv->count_is_enabled[count->id] = true;
508-
mutex_unlock(&priv->lock);
509511
} else {
510-
mutex_lock(&priv->lock);
511512
rz_mtu3_terminate_counter(counter, count->id);
512513
priv->count_is_enabled[count->id] = false;
513-
pm_runtime_put(ch->dev);
514-
mutex_unlock(&priv->lock);
514+
pm_runtime_put(counter->parent);
515515
}
516516

517+
exit:
518+
mutex_unlock(&priv->lock);
519+
517520
return ret;
518521
}
519522

@@ -540,9 +543,9 @@ static int rz_mtu3_cascade_counts_enable_get(struct counter_device *counter,
540543
if (ret)
541544
return ret;
542545

543-
pm_runtime_get_sync(priv->ch->dev);
546+
pm_runtime_get_sync(counter->parent);
544547
tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
545-
pm_runtime_put(priv->ch->dev);
548+
pm_runtime_put(counter->parent);
546549
*cascade_enable = test_bit(RZ_MTU3_TMDR3_LWA, &tmdr);
547550
mutex_unlock(&priv->lock);
548551

@@ -559,10 +562,10 @@ static int rz_mtu3_cascade_counts_enable_set(struct counter_device *counter,
559562
if (ret)
560563
return ret;
561564

562-
pm_runtime_get_sync(priv->ch->dev);
565+
pm_runtime_get_sync(counter->parent);
563566
rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3,
564567
RZ_MTU3_TMDR3_LWA, cascade_enable);
565-
pm_runtime_put(priv->ch->dev);
568+
pm_runtime_put(counter->parent);
566569
mutex_unlock(&priv->lock);
567570

568571
return 0;
@@ -579,9 +582,9 @@ static int rz_mtu3_ext_input_phase_clock_select_get(struct counter_device *count
579582
if (ret)
580583
return ret;
581584

582-
pm_runtime_get_sync(priv->ch->dev);
585+
pm_runtime_get_sync(counter->parent);
583586
tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
584-
pm_runtime_put(priv->ch->dev);
587+
pm_runtime_put(counter->parent);
585588
*ext_input_phase_clock_select = test_bit(RZ_MTU3_TMDR3_PHCKSEL, &tmdr);
586589
mutex_unlock(&priv->lock);
587590

@@ -598,11 +601,11 @@ static int rz_mtu3_ext_input_phase_clock_select_set(struct counter_device *count
598601
if (ret)
599602
return ret;
600603

601-
pm_runtime_get_sync(priv->ch->dev);
604+
pm_runtime_get_sync(counter->parent);
602605
rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3,
603606
RZ_MTU3_TMDR3_PHCKSEL,
604607
ext_input_phase_clock_select);
605-
pm_runtime_put(priv->ch->dev);
608+
pm_runtime_put(counter->parent);
606609
mutex_unlock(&priv->lock);
607610

608611
return 0;
@@ -640,7 +643,7 @@ static int rz_mtu3_action_read(struct counter_device *counter,
640643
if (ret)
641644
return ret;
642645

643-
ret = rz_mtu3_count_function_read_helper(ch, priv, &function);
646+
ret = rz_mtu3_count_function_read_helper(ch, counter, &function);
644647
if (ret) {
645648
mutex_unlock(&priv->lock);
646649
return ret;

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