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Yixun Lan
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riscv: dts: spacemit: k3: add full resource to UART
Previously the UART rely on external bootloader to initialize clock, pinctrl and reset, to solve this, explicitly adding those resource in Device Tree, so UART driver will handle them properly. Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-4-50a0aa53a245@kernel.org Signed-off-by: Yixun Lan <dlan@kernel.org>
1 parent 20b7792 commit 28a7f75

3 files changed

Lines changed: 68 additions & 10 deletions

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‎arch/riscv/boot/dts/spacemit/k3-pico-itx.dts‎

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Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
*/
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77
#include "k3.dtsi"
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#include "k3-pinctrl.dtsi"
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/ {
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model = "SpacemiT K3 Pico-ITX";
@@ -25,5 +26,7 @@
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_0_cfg>;
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status = "okay";
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};

‎arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi‎

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@@ -0,0 +1,24 @@
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (c) 2026 Yixun Lan <dlan@kernel.org>
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*/
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#include <dt-bindings/gpio/gpio.h>
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8+
#define K3_PADCONF(pin, func) (((pin) << 16) | (func))
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/* Map GPIO pin to each bank's <index, offset> */
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#define K3_GPIO(x) (x / 32) (x % 32)
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&pinctrl {
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/omit-if-no-ref/
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uart0_0_cfg: uart0-0-cfg {
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uart0-0-pins {
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pinmux = <K3_PADCONF(149, 2)>, /* uart0 tx */
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<K3_PADCONF(150, 2)>; /* uart0 rx */
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bias-pull-up = <0>;
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drive-strength = <25>;
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};
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};
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};

‎arch/riscv/boot/dts/spacemit/k3.dtsi‎

Lines changed: 41 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
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*/
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#include <dt-bindings/clock/spacemit,k3-clocks.h>
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#include <dt-bindings/reset/spacemit,k3-resets.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/dts-v1/;
@@ -451,7 +452,10 @@
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reg = <0x0 0xd4017000 0x0 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
454-
clock-frequency = <14700000>;
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clocks = <&syscon_apbc CLK_APBC_UART0>,
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<&syscon_apbc CLK_APBC_UART0_BUS>;
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clock-names = "core", "bus";
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resets = <&syscon_apbc RESET_APBC_UART0>;
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
457461
};
@@ -461,7 +465,10 @@
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reg = <0x0 0xd4017100 0x0 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
464-
clock-frequency = <14700000>;
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clocks = <&syscon_apbc CLK_APBC_UART2>,
469+
<&syscon_apbc CLK_APBC_UART2_BUS>;
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clock-names = "core", "bus";
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resets = <&syscon_apbc RESET_APBC_UART2>;
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interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
@@ -471,7 +478,10 @@
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reg = <0x0 0xd4017200 0x0 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
474-
clock-frequency = <14700000>;
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clocks = <&syscon_apbc CLK_APBC_UART3>,
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<&syscon_apbc CLK_APBC_UART3_BUS>;
483+
clock-names = "core", "bus";
484+
resets = <&syscon_apbc RESET_APBC_UART3>;
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interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
@@ -481,7 +491,10 @@
481491
reg = <0x0 0xd4017300 0x0 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
484-
clock-frequency = <14700000>;
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clocks = <&syscon_apbc CLK_APBC_UART4>,
495+
<&syscon_apbc CLK_APBC_UART4_BUS>;
496+
clock-names = "core", "bus";
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resets = <&syscon_apbc RESET_APBC_UART4>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
@@ -491,7 +504,10 @@
491504
reg = <0x0 0xd4017400 0x0 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
494-
clock-frequency = <14700000>;
507+
clocks = <&syscon_apbc CLK_APBC_UART5>,
508+
<&syscon_apbc CLK_APBC_UART5_BUS>;
509+
clock-names = "core", "bus";
510+
resets = <&syscon_apbc RESET_APBC_UART5>;
495511
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
496512
status = "disabled";
497513
};
@@ -501,7 +517,10 @@
501517
reg = <0x0 0xd4017500 0x0 0x100>;
502518
reg-shift = <2>;
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reg-io-width = <4>;
504-
clock-frequency = <14700000>;
520+
clocks = <&syscon_apbc CLK_APBC_UART6>,
521+
<&syscon_apbc CLK_APBC_UART6_BUS>;
522+
clock-names = "core", "bus";
523+
resets = <&syscon_apbc RESET_APBC_UART6>;
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interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
506525
status = "disabled";
507526
};
@@ -511,7 +530,10 @@
511530
reg = <0x0 0xd4017600 0x0 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
514-
clock-frequency = <14700000>;
533+
clocks = <&syscon_apbc CLK_APBC_UART7>,
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<&syscon_apbc CLK_APBC_UART7_BUS>;
535+
clock-names = "core", "bus";
536+
resets = <&syscon_apbc RESET_APBC_UART7>;
515537
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
516538
status = "disabled";
517539
};
@@ -521,7 +543,10 @@
521543
reg = <0x0 0xd4017700 0x0 0x100>;
522544
reg-shift = <2>;
523545
reg-io-width = <4>;
524-
clock-frequency = <14700000>;
546+
clocks = <&syscon_apbc CLK_APBC_UART8>,
547+
<&syscon_apbc CLK_APBC_UART8_BUS>;
548+
clock-names = "core", "bus";
549+
resets = <&syscon_apbc RESET_APBC_UART8>;
525550
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
526551
status = "disabled";
527552
};
@@ -531,7 +556,10 @@
531556
reg = <0x0 0xd4017800 0x0 0x100>;
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reg-shift = <2>;
533558
reg-io-width = <4>;
534-
clock-frequency = <14700000>;
559+
clocks = <&syscon_apbc CLK_APBC_UART9>,
560+
<&syscon_apbc CLK_APBC_UART9_BUS>;
561+
clock-names = "core", "bus";
562+
resets = <&syscon_apbc RESET_APBC_UART9>;
535563
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
536564
status = "disabled";
537565
};
@@ -567,7 +595,10 @@
567595
reg = <0x0 0xd401f000 0x0 0x100>;
568596
reg-shift = <2>;
569597
reg-io-width = <4>;
570-
clock-frequency = <14700000>;
598+
clocks = <&syscon_apbc CLK_APBC_UART10>,
599+
<&syscon_apbc CLK_APBC_UART10_BUS>;
600+
clock-names = "core", "bus";
601+
resets = <&syscon_apbc RESET_APBC_UART10>;
571602
interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
572603
status = "disabled";
573604
};

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