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Lijo Lazaralexdeucher
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drm/amd/pm: Use emit clock levels in SMU v15.0.0
print_clk_levels is no longer used, use emit_clk_levels instead. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 9163fe4 commit 22d6d1b

1 file changed

Lines changed: 18 additions & 15 deletions

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drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

Lines changed: 18 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -883,15 +883,14 @@ static int smu_v15_0_common_get_dpm_level_count(struct smu_context *smu,
883883
return 0;
884884
}
885885

886-
static int smu_v15_0_0_print_clk_levels(struct smu_context *smu,
887-
enum smu_clk_type clk_type, char *buf)
886+
static int smu_v15_0_0_emit_clk_levels(struct smu_context *smu,
887+
enum smu_clk_type clk_type, char *buf,
888+
int *offset)
888889
{
889-
int i, idx, ret = 0, size = 0;
890+
int i, idx, ret = 0, size = *offset;
890891
uint32_t cur_value = 0, value = 0, count = 0;
891892
uint32_t min, max;
892893

893-
smu_cmn_get_sysfs_buf(&buf, &size);
894-
895894
switch (clk_type) {
896895
case SMU_OD_SCLK:
897896
size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
@@ -915,27 +914,28 @@ static int smu_v15_0_0_print_clk_levels(struct smu_context *smu,
915914
case SMU_FCLK:
916915
ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
917916
if (ret)
918-
break;
917+
return ret;
919918

920919
ret = smu_v15_0_common_get_dpm_level_count(smu, clk_type, &count);
921920
if (ret)
922-
break;
921+
return ret;
923922

924923
for (i = 0; i < count; i++) {
925924
idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
926925
ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
927926
if (ret)
928-
break;
927+
return ret;
929928

930-
size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
929+
size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
930+
value,
931931
cur_value == value ? "*" : "");
932932
}
933933
break;
934934
case SMU_GFXCLK:
935935
case SMU_SCLK:
936936
ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
937937
if (ret)
938-
break;
938+
return ret;
939939
min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
940940
max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
941941
if (cur_value == max)
@@ -946,17 +946,20 @@ static int smu_v15_0_0_print_clk_levels(struct smu_context *smu,
946946
i = 1;
947947
size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
948948
i == 0 ? "*" : "");
949-
size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
950-
i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */
951-
i == 1 ? "*" : "");
949+
size += sysfs_emit_at(
950+
buf, size, "1: %uMhz %s\n",
951+
i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */
952+
i == 1 ? "*" : "");
952953
size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
953954
i == 2 ? "*" : "");
954955
break;
955956
default:
956957
break;
957958
}
958959

959-
return size;
960+
*offset = size;
961+
962+
return 0;
960963
}
961964

962965
static int smu_v15_0_0_set_soft_freq_limited_range(struct smu_context *smu,
@@ -1321,7 +1324,7 @@ static const struct pptable_funcs smu_v15_0_0_ppt_funcs = {
13211324
.mode2_reset = smu_v15_0_0_mode2_reset,
13221325
.get_dpm_ultimate_freq = smu_v15_0_common_get_dpm_ultimate_freq,
13231326
.od_edit_dpm_table = smu_v15_0_od_edit_dpm_table,
1324-
.print_clk_levels = smu_v15_0_0_print_clk_levels,
1327+
.emit_clk_levels = smu_v15_0_0_emit_clk_levels,
13251328
.force_clk_levels = smu_v15_0_0_force_clk_levels,
13261329
.set_performance_level = smu_v15_0_common_set_performance_level,
13271330
.set_fine_grain_gfx_freq_parameters = smu_v15_0_common_set_fine_grain_gfx_freq_parameters,

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