2323#define PIN_NAME_LEN 10
2424#define PAD_REG_OFF 0x100
2525
26- static void eqbr_gpio_disable_irq (struct irq_data * d )
26+ static void eqbr_irq_mask (struct irq_data * d )
2727{
2828 struct gpio_chip * gc = irq_data_get_irq_chip_data (d );
2929 struct eqbr_gpio_ctrl * gctrl = gpiochip_get_data (gc );
@@ -36,7 +36,7 @@ static void eqbr_gpio_disable_irq(struct irq_data *d)
3636 gpiochip_disable_irq (gc , offset );
3737}
3838
39- static void eqbr_gpio_enable_irq (struct irq_data * d )
39+ static void eqbr_irq_unmask (struct irq_data * d )
4040{
4141 struct gpio_chip * gc = irq_data_get_irq_chip_data (d );
4242 struct eqbr_gpio_ctrl * gctrl = gpiochip_get_data (gc );
@@ -50,7 +50,7 @@ static void eqbr_gpio_enable_irq(struct irq_data *d)
5050 raw_spin_unlock_irqrestore (& gctrl -> lock , flags );
5151}
5252
53- static void eqbr_gpio_ack_irq (struct irq_data * d )
53+ static void eqbr_irq_ack (struct irq_data * d )
5454{
5555 struct gpio_chip * gc = irq_data_get_irq_chip_data (d );
5656 struct eqbr_gpio_ctrl * gctrl = gpiochip_get_data (gc );
@@ -62,10 +62,10 @@ static void eqbr_gpio_ack_irq(struct irq_data *d)
6262 raw_spin_unlock_irqrestore (& gctrl -> lock , flags );
6363}
6464
65- static void eqbr_gpio_mask_ack_irq (struct irq_data * d )
65+ static void eqbr_irq_mask_ack (struct irq_data * d )
6666{
67- eqbr_gpio_disable_irq (d );
68- eqbr_gpio_ack_irq (d );
67+ eqbr_irq_mask (d );
68+ eqbr_irq_ack (d );
6969}
7070
7171static inline void eqbr_cfg_bit (void __iomem * addr ,
@@ -92,7 +92,7 @@ static int eqbr_irq_type_cfg(struct gpio_irq_type *type,
9292 return 0 ;
9393}
9494
95- static int eqbr_gpio_set_irq_type (struct irq_data * d , unsigned int type )
95+ static int eqbr_irq_set_type (struct irq_data * d , unsigned int type )
9696{
9797 struct gpio_chip * gc = irq_data_get_irq_chip_data (d );
9898 struct eqbr_gpio_ctrl * gctrl = gpiochip_get_data (gc );
@@ -166,11 +166,11 @@ static void eqbr_irq_handler(struct irq_desc *desc)
166166
167167static const struct irq_chip eqbr_irq_chip = {
168168 .name = "gpio_irq" ,
169- .irq_mask = eqbr_gpio_disable_irq ,
170- .irq_unmask = eqbr_gpio_enable_irq ,
171- .irq_ack = eqbr_gpio_ack_irq ,
172- .irq_mask_ack = eqbr_gpio_mask_ack_irq ,
173- .irq_set_type = eqbr_gpio_set_irq_type ,
169+ .irq_ack = eqbr_irq_ack ,
170+ .irq_mask = eqbr_irq_mask ,
171+ .irq_mask_ack = eqbr_irq_mask_ack ,
172+ .irq_unmask = eqbr_irq_unmask ,
173+ .irq_set_type = eqbr_irq_set_type ,
174174 .flags = IRQCHIP_IMMUTABLE ,
175175 GPIOCHIP_IRQ_RESOURCE_HELPERS ,
176176};
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