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Lijo Lazaralexdeucher
Lijo Lazar
authored and
alexdeucher
committed
drm/amd/pm: Initialize allowed feature list
Instead of returning feature bit mask of allowed features, initialize the allowed features in the callback implementation itself. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 156c0ab commit 0d9a49a

11 files changed

Lines changed: 158 additions & 226 deletions

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‎drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c‎

Lines changed: 3 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -691,11 +691,8 @@ static int smu_sys_set_pp_table(void *handle,
691691
return ret;
692692
}
693693

694-
static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
694+
static int smu_init_driver_allowed_feature_mask(struct smu_context *smu)
695695
{
696-
uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
697-
int ret = 0;
698-
699696
/*
700697
* With SCPM enabled, the allowed featuremasks setting(via
701698
* PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
@@ -710,15 +707,7 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
710707

711708
smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
712709

713-
ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
714-
SMU_FEATURE_MAX/32);
715-
if (ret)
716-
return ret;
717-
718-
smu_feature_list_add_bits(smu, SMU_FEATURE_LIST_ALLOWED,
719-
(unsigned long *)allowed_feature_mask);
720-
721-
return ret;
710+
return smu_init_allowed_features(smu);
722711
}
723712

724713
static int smu_set_funcs(struct amdgpu_device *adev)
@@ -1949,7 +1938,7 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block)
19491938
if (!smu->pm_enabled)
19501939
return 0;
19511940

1952-
ret = smu_get_driver_allowed_feature_mask(smu);
1941+
ret = smu_init_driver_allowed_feature_mask(smu);
19531942
if (ret)
19541943
return ret;
19551944

‎drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h‎

Lines changed: 3 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -812,11 +812,10 @@ struct pptable_funcs {
812812
int (*run_btc)(struct smu_context *smu);
813813

814814
/**
815-
* @get_allowed_feature_mask: Get allowed feature mask.
816-
* &feature_mask: Array to store feature mask.
817-
* &num: Elements in &feature_mask.
815+
* @init_allowed_features: Initialize allowed features bitmap.
816+
* Directly sets allowed features using smu_feature wrapper functions.
818817
*/
819-
int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
818+
int (*init_allowed_features)(struct smu_context *smu);
820819

821820
/**
822821
* @get_current_power_state: Get the current power state.
@@ -2052,14 +2051,6 @@ static inline void smu_feature_bits_copy(struct smu_feature_bits *dst,
20522051
bitmap_copy(dst->bits, src, nbits);
20532052
}
20542053

2055-
static inline void smu_feature_bits_or(struct smu_feature_bits *dst,
2056-
const struct smu_feature_bits *src1,
2057-
const unsigned long *src2,
2058-
unsigned int nbits)
2059-
{
2060-
bitmap_or(dst->bits, src1->bits, src2, nbits);
2061-
}
2062-
20632054
static inline struct smu_feature_bits *
20642055
__smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list)
20652056
{
@@ -2128,15 +2119,6 @@ static inline void smu_feature_list_set_bits(struct smu_context *smu,
21282119
smu->smu_feature.feature_num);
21292120
}
21302121

2131-
static inline void smu_feature_list_add_bits(struct smu_context *smu,
2132-
enum smu_feature_list list,
2133-
const unsigned long *src)
2134-
{
2135-
struct smu_feature_bits *bits = __smu_feature_get_list(smu, list);
2136-
2137-
smu_feature_bits_or(bits, bits, src, smu->smu_feature.feature_num);
2138-
}
2139-
21402122
static inline void smu_feature_list_to_arr32(struct smu_context *smu,
21412123
enum smu_feature_list list,
21422124
uint32_t *arr)

‎drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c‎

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -345,14 +345,9 @@ static int arcturus_init_smc_tables(struct smu_context *smu)
345345
}
346346

347347
static int
348-
arcturus_get_allowed_feature_mask(struct smu_context *smu,
349-
uint32_t *feature_mask, uint32_t num)
348+
arcturus_init_allowed_features(struct smu_context *smu)
350349
{
351-
if (num > 2)
352-
return -EINVAL;
353-
354-
/* pptable will handle the features to enable */
355-
memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
350+
smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
356351

357352
return 0;
358353
}
@@ -1877,7 +1872,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
18771872

18781873
static const struct pptable_funcs arcturus_ppt_funcs = {
18791874
/* init dpm */
1880-
.get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
1875+
.init_allowed_features = arcturus_init_allowed_features,
18811876
/* btc */
18821877
.run_btc = arcturus_run_btc,
18831878
/* dpm/clk tables */

‎drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c‎

Lines changed: 43 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -275,89 +275,83 @@ static bool is_asic_secure(struct smu_context *smu)
275275
}
276276

277277
static int
278-
navi10_get_allowed_feature_mask(struct smu_context *smu,
279-
uint32_t *feature_mask, uint32_t num)
278+
navi10_init_allowed_features(struct smu_context *smu)
280279
{
281280
struct amdgpu_device *adev = smu->adev;
282281

283-
if (num > 2)
284-
return -EINVAL;
285-
286-
memset(feature_mask, 0, sizeof(uint32_t) * num);
287-
288-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
289-
| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
290-
| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
291-
| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
292-
| FEATURE_MASK(FEATURE_PPT_BIT)
293-
| FEATURE_MASK(FEATURE_TDC_BIT)
294-
| FEATURE_MASK(FEATURE_GFX_EDC_BIT)
295-
| FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
296-
| FEATURE_MASK(FEATURE_VR0HOT_BIT)
297-
| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
298-
| FEATURE_MASK(FEATURE_THERMAL_BIT)
299-
| FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
300-
| FEATURE_MASK(FEATURE_DS_LCLK_BIT)
301-
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
302-
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
303-
| FEATURE_MASK(FEATURE_BACO_BIT)
304-
| FEATURE_MASK(FEATURE_GFX_SS_BIT)
305-
| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
306-
| FEATURE_MASK(FEATURE_FW_CTF_BIT)
307-
| FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)
308-
| FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT);
282+
smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
283+
284+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT);
285+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
286+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT);
287+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
288+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT);
289+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT);
290+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_EDC_BIT);
291+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_PLUS_BIT);
292+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
293+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
294+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT);
295+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_LED_DISPLAY_BIT);
296+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
297+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT);
298+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
299+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
300+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT);
301+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT);
302+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
303+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT);
304+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TEMP_DEPENDENT_VMIN_BIT);
309305

310306
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
311-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
307+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
312308

313309
if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
314-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
310+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
315311

316312
if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
317-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
313+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT);
318314

319315
if (adev->pm.pp_feature & PP_ULV_MASK)
320-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
316+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
321317

322318
if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
319+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
324320

325321
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
322+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
327323

328324
if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
329-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
325+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT);
330326

331327
if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
332-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
328+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT);
333329

334330
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
335-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
331+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VCN_PG_BIT);
336332

337333
if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
338-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
334+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_JPEG_PG_BIT);
339335

340336
if (smu->dc_controlled_by_gpio)
341-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
337+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT);
342338

343339
if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
344-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
340+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
345341

346-
/* DPM UCLK enablement should be skipped for navi10 A0 secure board */
347342
if (!(is_asic_secure(smu) &&
348343
(amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
349344
(adev->rev_id == 0)) &&
350-
(adev->pm.pp_feature & PP_MCLK_DPM_MASK))
351-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
352-
| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
353-
| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
345+
(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
346+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
347+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);
348+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
349+
}
354350

355-
/* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
356351
if (is_asic_secure(smu) &&
357352
(amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
358353
(adev->rev_id == 0))
359-
*(uint64_t *)feature_mask &=
360-
~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
354+
smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
361355

362356
return 0;
363357
}
@@ -3277,7 +3271,7 @@ static int navi10_set_config_table(struct smu_context *smu,
32773271
}
32783272

32793273
static const struct pptable_funcs navi10_ppt_funcs = {
3280-
.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3274+
.init_allowed_features = navi10_init_allowed_features,
32813275
.set_default_dpm_table = navi10_set_default_dpm_table,
32823276
.dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
32833277
.dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,

‎drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c‎

Lines changed: 43 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -276,85 +276,82 @@ static const uint8_t sienna_cichlid_throttler_map[] = {
276276
};
277277

278278
static int
279-
sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
280-
uint32_t *feature_mask, uint32_t num)
279+
sienna_cichlid_init_allowed_features(struct smu_context *smu)
281280
{
282281
struct amdgpu_device *adev = smu->adev;
283282

284-
if (num > 2)
285-
return -EINVAL;
286-
287-
memset(feature_mask, 0, sizeof(uint32_t) * num);
288-
289-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
290-
| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
291-
| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
292-
| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
293-
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
294-
| FEATURE_MASK(FEATURE_DS_FCLK_BIT)
295-
| FEATURE_MASK(FEATURE_DS_UCLK_BIT)
296-
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
297-
| FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
298-
| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
299-
| FEATURE_MASK(FEATURE_GFX_SS_BIT)
300-
| FEATURE_MASK(FEATURE_VR0HOT_BIT)
301-
| FEATURE_MASK(FEATURE_PPT_BIT)
302-
| FEATURE_MASK(FEATURE_TDC_BIT)
303-
| FEATURE_MASK(FEATURE_BACO_BIT)
304-
| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
305-
| FEATURE_MASK(FEATURE_FW_CTF_BIT)
306-
| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
307-
| FEATURE_MASK(FEATURE_THERMAL_BIT)
308-
| FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
283+
smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
284+
285+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT);
286+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT);
287+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
288+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
289+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT);
290+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT);
291+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_UCLK_BIT);
292+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
293+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT);
294+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT);
295+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT);
296+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
297+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT);
298+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT);
299+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
300+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT);
301+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
302+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
303+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT);
304+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT);
309305

310306
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
311-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
307+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
308+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_GPO_BIT);
313309
}
314310

315311
if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
316312
(amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) &&
317313
!(adev->flags & AMD_IS_APU))
318-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
314+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_DCS_BIT);
319315

320-
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
321-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
322-
| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
323-
| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
316+
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
317+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
318+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);
319+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
320+
}
324321

325322
if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
326-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
323+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
327324

328325
if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
329-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
326+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT);
330327

331328
if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
332-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
329+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
333330

334331
if (adev->pm.pp_feature & PP_ULV_MASK)
335-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
332+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
336333

337334
if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
338-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
335+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
339336

340337
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
341-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
338+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
342339

343340
if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
344-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
341+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT);
345342

346343
if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
347-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
344+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT);
348345

349346
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
350347
smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
351-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
348+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_PG_BIT);
352349

353350
if (smu->dc_controlled_by_gpio)
354-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
351+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT);
355352

356353
if (amdgpu_device_should_use_aspm(adev))
357-
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
354+
smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
358355

359356
return 0;
360357
}
@@ -3085,7 +3082,7 @@ static int sienna_cichlid_mode2_reset(struct smu_context *smu)
30853082
}
30863083

30873084
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
3088-
.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3085+
.init_allowed_features = sienna_cichlid_init_allowed_features,
30893086
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
30903087
.dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
30913088
.dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,

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