Skip to content

Commit 07f7d0f

Browse files
committed
Merge branch 'pci/controller/dwc-qcom'
- Advertise 'Hot-Plug Capable' and set 'No Command Completed Support' since Qcom Root Ports support hotplug events like DL_Up/Down and can accept writes to Slot Control without delays between writes (Krishna Chaitanya Chundru) * pci/controller/dwc-qcom: PCI: qcom: Advertise Hotplug Slot Capability with no Command Completion support
2 parents b94fd08 + 33a76fc commit 07f7d0f

1 file changed

Lines changed: 11 additions & 6 deletions

File tree

drivers/pci/controller/dwc/pcie-qcom.c

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -350,15 +350,20 @@ static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci)
350350
dw_pcie_dbi_ro_wr_dis(pci);
351351
}
352352

353-
static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
353+
static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci)
354354
{
355355
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
356356
u32 val;
357357

358358
dw_pcie_dbi_ro_wr_en(pci);
359359

360+
/*
361+
* Qcom PCIe Root Ports do not support generating command completion
362+
* notifications for the Hot-Plug commands. So set the NCCS field to
363+
* avoid waiting for the completions.
364+
*/
360365
val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
361-
val &= ~PCI_EXP_SLTCAP_HPC;
366+
val |= PCI_EXP_SLTCAP_NCCS;
362367
writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
363368

364369
dw_pcie_dbi_ro_wr_dis(pci);
@@ -558,7 +563,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
558563
writel(CFG_BRIDGE_SB_INIT,
559564
pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1);
560565

561-
qcom_pcie_clear_hpc(pcie->pci);
566+
qcom_pcie_set_slot_nccs(pcie->pci);
562567

563568
return 0;
564569
}
@@ -638,7 +643,7 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
638643
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
639644
}
640645

641-
qcom_pcie_clear_hpc(pcie->pci);
646+
qcom_pcie_set_slot_nccs(pcie->pci);
642647

643648
return 0;
644649
}
@@ -731,7 +736,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
731736
val |= EN;
732737
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
733738

734-
qcom_pcie_clear_hpc(pcie->pci);
739+
qcom_pcie_set_slot_nccs(pcie->pci);
735740

736741
return 0;
737742
}
@@ -1037,7 +1042,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
10371042
writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
10381043
pcie->parf + PARF_NO_SNOOP_OVERRIDE);
10391044

1040-
qcom_pcie_clear_hpc(pcie->pci);
1045+
qcom_pcie_set_slot_nccs(pcie->pci);
10411046

10421047
return 0;
10431048
}

0 commit comments

Comments
 (0)