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100 | 100 | #define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025 |
101 | 101 | #define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026 |
102 | 102 |
|
| 103 | +#define PCI_VENDOR_ID_SYSTEMBASE 0x14a1 |
| 104 | + |
103 | 105 | /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ |
104 | 106 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 |
105 | 107 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 |
@@ -2128,6 +2130,35 @@ pci_moxa_setup(struct serial_private *priv, |
2128 | 2130 | return setup_port(priv, port, bar, offset, 0); |
2129 | 2131 | } |
2130 | 2132 |
|
| 2133 | +#define SB_OPTR_IMR0 0x0c /* Interrupt mask register, p0 to p7 */ |
| 2134 | +static int pci_systembase_init(struct pci_dev *dev) |
| 2135 | +{ |
| 2136 | + resource_size_t iobase; |
| 2137 | + |
| 2138 | + if (!IS_ENABLED(CONFIG_HAS_IOPORT)) |
| 2139 | + return serial_8250_warn_need_ioport(dev); |
| 2140 | + |
| 2141 | + iobase = pci_resource_start(dev, 1); |
| 2142 | + |
| 2143 | + /* This will support up to 8 ports */ |
| 2144 | + outb(0xff, iobase + SB_OPTR_IMR0); |
| 2145 | + |
| 2146 | + return 0; |
| 2147 | +} |
| 2148 | + |
| 2149 | +static void pci_systembase_exit(struct pci_dev *dev) |
| 2150 | +{ |
| 2151 | + resource_size_t iobase; |
| 2152 | + |
| 2153 | + if (!IS_ENABLED(CONFIG_HAS_IOPORT)) { |
| 2154 | + serial_8250_warn_need_ioport(dev); |
| 2155 | + return; |
| 2156 | + } |
| 2157 | + |
| 2158 | + iobase = pci_resource_start(dev, 0); |
| 2159 | + outb(0x00, iobase + SB_OPTR_IMR0); |
| 2160 | +} |
| 2161 | + |
2131 | 2162 | /* |
2132 | 2163 | * Master list of serial port init/setup/exit quirks. |
2133 | 2164 | * This does not describe the general nature of the port. |
@@ -2476,6 +2507,16 @@ static struct pci_serial_quirk pci_serial_quirks[] = { |
2476 | 2507 | .init = pci_siig_init, |
2477 | 2508 | .setup = pci_siig_setup, |
2478 | 2509 | }, |
| 2510 | + /* Systembase */ |
| 2511 | + { |
| 2512 | + .vendor = PCI_VENDOR_ID_SYSTEMBASE, |
| 2513 | + .device = 0x0008, |
| 2514 | + .subvendor = PCI_ANY_ID, |
| 2515 | + .subdevice = PCI_ANY_ID, |
| 2516 | + .init = pci_systembase_init, |
| 2517 | + .setup = pci_default_setup, |
| 2518 | + .exit = pci_systembase_exit, |
| 2519 | + }, |
2479 | 2520 | /* |
2480 | 2521 | * Titan cards |
2481 | 2522 | */ |
@@ -3041,6 +3082,7 @@ enum pci_board_num_t { |
3041 | 3082 | pbn_b0_1_921600, |
3042 | 3083 | pbn_b0_2_921600, |
3043 | 3084 | pbn_b0_4_921600, |
| 3085 | + pbn_b0_8_921600, |
3044 | 3086 |
|
3045 | 3087 | pbn_b0_2_1130000, |
3046 | 3088 |
|
@@ -3241,6 +3283,12 @@ static struct pciserial_board pci_boards[] = { |
3241 | 3283 | .base_baud = 921600, |
3242 | 3284 | .uart_offset = 8, |
3243 | 3285 | }, |
| 3286 | + [pbn_b0_8_921600] = { |
| 3287 | + .flags = FL_BASE0, |
| 3288 | + .num_ports = 8, |
| 3289 | + .base_baud = 921600, |
| 3290 | + .uart_offset = 8, |
| 3291 | + }, |
3244 | 3292 |
|
3245 | 3293 | [pbn_b0_2_1130000] = { |
3246 | 3294 | .flags = FL_BASE0, |
@@ -6152,6 +6200,9 @@ static const struct pci_device_id serial_pci_tbl[] = { |
6152 | 6200 | PCI_ANY_ID, PCI_ANY_ID, |
6153 | 6201 | 0, 0, pbn_b0_1_115200 }, |
6154 | 6202 |
|
| 6203 | + /* Systembase Multi I/O cards */ |
| 6204 | + { PCI_VDEVICE(SYSTEMBASE, 0x0008), pbn_b0_8_921600 }, |
| 6205 | + |
6155 | 6206 | /* Fintek PCI serial cards */ |
6156 | 6207 | { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, |
6157 | 6208 | { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, |
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