Skip to content

Commit 005b25a

Browse files
Suneel Garapatipateldipen1984-nv
Suneel Garapati
authored and
pateldipen1984-nv
committed
hte: tegra194: Add Tegra264 GTE support
Add AON-GTE mapping and LIC GTE instance support for the Tegra264. Move TSC clock parameters from macros to members of SoC data as values differ for Tegra264 chip. Signed-off-by: Suneel Garapati <suneelg@nvidia.com> Reviewed-by: Dipen Patel <dipenp@nvidia.com> Signed-off-by: Dipen Patel <dipenp@nvidia.com>
1 parent d354e47 commit 005b25a

1 file changed

Lines changed: 128 additions & 5 deletions

File tree

‎drivers/hte/hte-tegra194.c‎

Lines changed: 128 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -20,10 +20,11 @@
2020

2121
#define HTE_SUSPEND 0
2222

23-
/* HTE source clock TSC is 31.25MHz */
23+
/* HTE source clock TSC is 1GHz for T264 and 31.25MHz for others */
2424
#define HTE_TS_CLK_RATE_HZ 31250000ULL
25+
#define HTE_TS_CLK_RATE_1G 1000000000ULL
2526
#define HTE_CLK_RATE_NS 32
26-
#define HTE_TS_NS_SHIFT __builtin_ctz(HTE_CLK_RATE_NS)
27+
#define HTE_CLK_RATE_NS_1G 1
2728

2829
#define NV_AON_SLICE_INVALID -1
2930
#define NV_LINES_IN_SLICE 32
@@ -120,6 +121,8 @@ struct tegra_hte_data {
120121
u32 slices;
121122
u32 map_sz;
122123
u32 sec_map_sz;
124+
u64 tsc_clkrate_hz;
125+
u32 tsc_clkrate_ns;
123126
const struct tegra_hte_line_mapped *map;
124127
const struct tegra_hte_line_mapped *sec_map;
125128
};
@@ -317,13 +320,103 @@ static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = {
317320
[40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
318321
};
319322

323+
static const struct tegra_hte_line_mapped tegra264_aon_gpio_map[] = {
324+
/* gpio, slice, bit_index */
325+
/* AA port */
326+
[0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
327+
[1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
328+
[2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
329+
[3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
330+
[4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
331+
[5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
332+
[6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
333+
[7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
334+
/* BB port */
335+
[8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
336+
[9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
337+
/* CC port */
338+
[10] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
339+
[11] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
340+
[12] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
341+
[13] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
342+
[14] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
343+
[15] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
344+
[16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
345+
[17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
346+
/* DD port */
347+
[18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
348+
[19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
349+
[20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
350+
[21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
351+
[22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
352+
[23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
353+
[24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
354+
[25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
355+
/* EE port */
356+
[26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
357+
[27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
358+
[28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
359+
[29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
360+
};
361+
362+
static const struct tegra_hte_line_mapped tegra264_aon_gpio_sec_map[] = {
363+
/* gpio, slice, bit_index */
364+
/* AA port */
365+
[0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
366+
[1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
367+
[2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
368+
[3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
369+
[4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
370+
[5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
371+
[6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
372+
[7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
373+
/* BB port */
374+
[8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
375+
[9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
376+
[10] = {NV_AON_SLICE_INVALID, 0},
377+
[11] = {NV_AON_SLICE_INVALID, 0},
378+
[12] = {NV_AON_SLICE_INVALID, 0},
379+
[13] = {NV_AON_SLICE_INVALID, 0},
380+
[14] = {NV_AON_SLICE_INVALID, 0},
381+
[15] = {NV_AON_SLICE_INVALID, 0},
382+
/* CC port */
383+
[16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
384+
[17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
385+
[18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
386+
[19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
387+
[20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
388+
[21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
389+
[22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
390+
[23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
391+
/* DD port */
392+
[24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
393+
[25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
394+
[26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
395+
[27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
396+
[28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
397+
[29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
398+
[30] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
399+
[31] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
400+
/* EE port */
401+
[32] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
402+
[33] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
403+
[34] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
404+
[35] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
405+
[36] = {NV_AON_SLICE_INVALID, 0},
406+
[37] = {NV_AON_SLICE_INVALID, 0},
407+
[38] = {NV_AON_SLICE_INVALID, 0},
408+
[39] = {NV_AON_SLICE_INVALID, 0},
409+
};
410+
320411
static const struct tegra_hte_data t194_aon_hte = {
321412
.map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),
322413
.map = tegra194_aon_gpio_map,
323414
.sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map),
324415
.sec_map = tegra194_aon_gpio_sec_map,
325416
.type = HTE_TEGRA_TYPE_GPIO,
326417
.slices = 3,
418+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,
419+
.tsc_clkrate_ns = HTE_CLK_RATE_NS,
327420
};
328421

329422
static const struct tegra_hte_data t234_aon_hte = {
@@ -333,20 +426,46 @@ static const struct tegra_hte_data t234_aon_hte = {
333426
.sec_map = tegra234_aon_gpio_sec_map,
334427
.type = HTE_TEGRA_TYPE_GPIO,
335428
.slices = 3,
429+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,
430+
.tsc_clkrate_ns = HTE_CLK_RATE_NS,
431+
};
432+
433+
static const struct tegra_hte_data t264_aon_hte = {
434+
.map_sz = ARRAY_SIZE(tegra264_aon_gpio_map),
435+
.map = tegra264_aon_gpio_map,
436+
.sec_map_sz = ARRAY_SIZE(tegra264_aon_gpio_sec_map),
437+
.sec_map = tegra264_aon_gpio_sec_map,
438+
.type = HTE_TEGRA_TYPE_GPIO,
439+
.slices = 4,
440+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_1G,
441+
.tsc_clkrate_ns = HTE_CLK_RATE_NS_1G,
336442
};
337443

338444
static const struct tegra_hte_data t194_lic_hte = {
339445
.map_sz = 0,
340446
.map = NULL,
341447
.type = HTE_TEGRA_TYPE_LIC,
342448
.slices = 11,
449+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,
450+
.tsc_clkrate_ns = HTE_CLK_RATE_NS,
343451
};
344452

345453
static const struct tegra_hte_data t234_lic_hte = {
346454
.map_sz = 0,
347455
.map = NULL,
348456
.type = HTE_TEGRA_TYPE_LIC,
349457
.slices = 17,
458+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,
459+
.tsc_clkrate_ns = HTE_CLK_RATE_NS,
460+
};
461+
462+
static const struct tegra_hte_data t264_lic_hte = {
463+
.map_sz = 0,
464+
.map = NULL,
465+
.type = HTE_TEGRA_TYPE_LIC,
466+
.slices = 10,
467+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_1G,
468+
.tsc_clkrate_ns = HTE_CLK_RATE_NS_1G,
350469
};
351470

352471
static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg)
@@ -574,12 +693,12 @@ static int tegra_hte_release(struct hte_chip *chip, struct hte_ts_desc *desc,
574693
static int tegra_hte_clk_src_info(struct hte_chip *chip,
575694
struct hte_clk_info *ci)
576695
{
577-
(void)chip;
696+
struct tegra_hte_soc *hte_dev = chip->data;
578697

579698
if (!ci)
580699
return -EINVAL;
581700

582-
ci->hz = HTE_TS_CLK_RATE_HZ;
701+
ci->hz = hte_dev->prov_data->tsc_clkrate_hz;
583702
ci->type = CLOCK_MONOTONIC;
584703

585704
return 0;
@@ -602,8 +721,10 @@ static void tegra_hte_read_fifo(struct tegra_hte_soc *gs)
602721
{
603722
u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id;
604723
u64 tsc;
724+
u8 tsc_ns_shift;
605725
struct hte_ts_data el;
606726

727+
tsc_ns_shift = __builtin_ctz(gs->prov_data->tsc_clkrate_ns);
607728
while ((tegra_hte_readl(gs, HTE_TESTATUS) >>
608729
HTE_TESTATUS_OCCUPANCY_SHIFT) &
609730
HTE_TESTATUS_OCCUPANCY_MASK) {
@@ -621,7 +742,7 @@ static void tegra_hte_read_fifo(struct tegra_hte_soc *gs)
621742
while (acv) {
622743
bit_index = __builtin_ctz(acv);
623744
line_id = bit_index + (slice << 5);
624-
el.tsc = tsc << HTE_TS_NS_SHIFT;
745+
el.tsc = tsc << tsc_ns_shift;
625746
el.raw_level = tegra_hte_get_level(gs, line_id);
626747
hte_push_ts_ns(gs->chip, line_id, &el);
627748
acv &= ~BIT(bit_index);
@@ -656,6 +777,8 @@ static const struct of_device_id tegra_hte_of_match[] = {
656777
{ .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
657778
{ .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte},
658779
{ .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
780+
{ .compatible = "nvidia,tegra264-gte-lic", .data = &t264_lic_hte},
781+
{ .compatible = "nvidia,tegra264-gte-aon", .data = &t264_aon_hte},
659782
{ }
660783
};
661784
MODULE_DEVICE_TABLE(of, tegra_hte_of_match);

0 commit comments

Comments
 (0)