fix: speculative fix for CI failure

 Synchronize the instruction cache before running the TLBI trampoline.

Signed-off-by: Tomasz Andrzejak <andreiltd@gmail.com>

Author: andreiltd

src/hyperlight_host/src/hypervisor/virtual_machine/hvf/bindings.h

@@ -2,6 +2,7 @@
 // Copyright 2025 The Hyperlight Authors.
 
 #include <Hypervisor/Hypervisor.h>
+#include <libkern/OSCacheControl.h>
 
 hv_return_t
 hv_vcpu_get_simd_fp_reg_rsabi(hv_vcpu_t vcpu, hv_simd_fp_reg_t reg, char *val);

src/hyperlight_host/src/hypervisor/virtual_machine/hvf/mod.rs

@@ -764,6 +764,7 @@ struct TlbiRegion {
     insn_memory: ReadonlySharedMemory,
 }
 impl TlbiRegion {
+    /// Prepare the TLB-flush instructions for execution on any vCPU.
     fn new() -> Result<Self, SharedMemoryError> {
         let mut bytes = vec![0; page_size::get()];
         bytes[0..20].copy_from_slice(&[
@@ -773,9 +774,18 @@ impl TlbiRegion {
             0xdf, 0x3f, 0x03, 0xd5, // isb sy
             0x02, 0x00, 0x00, 0xd4, // hvc #0
         ]);
-        Ok(Self {
-            insn_memory: ReadonlySharedMemory::from_bytes(&bytes, page_size::get())?,
-        })
+        let insn_memory = ReadonlySharedMemory::from_bytes(&bytes, page_size::get())?;
+        let instructions = insn_memory.as_slice();
+
+        // SAFETY: The range is a live mapping. Cache maintenance completes before guest execution.
+        unsafe {
+            bindings::sys_icache_invalidate(
+                instructions.as_ptr().cast_mut().cast(),
+                instructions.len(),
+            );
+        }
+
+        Ok(Self { insn_memory })
     }
 }
 impl From<&TlbiRegion> for MemoryRegion {