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<?xml version="1.0" encoding="utf-8"?>
<feed xmlns="http://www.w3.org/2005/Atom">
<id>https://halftop.github.io</id>
<title>1/2顶点</title>
<updated>2019-11-07T01:28:12.470Z</updated>
<generator>https://github.com/jpmonette/feed</generator>
<link rel="alternate" href="https://halftop.github.io"/>
<link rel="self" href="https://halftop.github.io/atom.xml"/>
<subtitle> 有输入有输出，才是正确的学习方式 </subtitle>
<logo>https://halftop.github.io/images/avatar.png</logo>
<icon>https://halftop.github.io/favicon.ico</icon>
<rights>All rights reserved 2019, 1/2顶点</rights>
<entry>
<title type="html"><![CDATA[Kde Ubuntu 18.04安装笔记]]></title>
<id>https://halftop.github.io/post/note_for_ubuntu_18.04</id>
<link href="https://halftop.github.io/post/note_for_ubuntu_18.04">
</link>
<updated>2019-10-30T14:33:33.000Z</updated>
<content type="html"><![CDATA[<h2 id="安装设置">安装设置</h2>
<ul>
<li>语言选择英语，避免<code>/home</code>出现中文文件夹。</li>
<li>选择最小安装；勾选为图形或无线硬件，以及其它媒体格式安装第三方软件。</li>
<li>双系统安装，无需设置<code>/boot</code>分区，只许把选择把引导安装在<code>Windows Boot Manager</code>即<code>EFI</code>分区即可。</li>
<li>其它选项按字面意思常规处理即可。</li>
</ul>
<h2 id="更换软件源">更换软件源</h2>
<p><code>/etc/apt/sources.list</code></p>
<ul>
<li>
<p>ipv4 - <a href="https://linux.xidian.edu.cn/git/xdlinux/mirror-help/src/master/ubuntu.md">Xidian University</a></p>
<pre><code>deb http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic main restricted universe multiverse
#deb-src http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic main restricted universe multiverse
deb http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic-security main restricted universe multiverse
#deb-src http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic-security main restricted universe multiverse
deb http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic-updates main restricted universe multiverse
#deb-src http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic-updates main restricted universe multiverse
#deb http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic-backports main restricted universe multiverse
#deb-src http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic-backports main restricted universe multiverse
#deb http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic-proposed main restricted universe multiverse
#deb-src http://linux.xidian.edu.cn/mirrors/ubuntu/ bionic-proposed main restricted universe multiverse
</code></pre>
</li>
<li>
<p>ipv6 - <a href="https://mirrors.ustc.edu.cn/repogen/">USTC</a></p>
<pre><code>deb https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic main restricted universe multiverse
deb-src https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic main restricted universe multiverse
deb https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic-security main restricted universe multiverse
deb-src https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic-security main restricted universe multiverse
deb https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic-updates main restricted universe multiverse
deb-src https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic-updates main restricted universe multiverse
deb https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic-backports main restricted universe multiverse
deb-src https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic-backports main restricted universe multiverse
## Not recommended
# deb https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic-proposed main restricted universe multiverse
# deb-src https://ipv6.mirrors.ustc.edu.cn/ubuntu/ bionic-proposed main restricted universe multiverse
</code></pre>
</li>
<li>
<p>ipv6 - <a href="https://mirrors6.tuna.tsinghua.edu.cn">tsinghua</a></p>
<pre><code> # 默认注释了源码镜像以提高 apt update 速度，如有需要可自行取消注释
deb https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic main restricted universe multiverse
# deb-src https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic main restricted universe multiverse
deb https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic-updates main restricted universe multiverse
# deb-src https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic-updates main restricted universe multiverse
deb https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic-backports main restricted universe multiverse
# deb-src https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic-backports main restricted universe multiverse
deb https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic-security main restricted universe multiverse
# deb-src https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic-security main restricted universe multiverse
# 预发布软件源，不建议启用
# deb https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic-proposed main restricted universe multiverse
# deb-src https://mirrors6.tuna.tsinghua.edu.cn/ubuntu/ bionic-proposed main restricted universe multiverse
</code></pre>
</li>
</ul>
<h2 id="网络连接pppoe">网络连接（pppoe）</h2>
<p>主要是为了解决<code>Network Manager</code>中没有<code>PPPOE/DSL</code>选项而不能拨号的问题。</p>
<p>使用<code>Network Manager</code>工具中<a href="https://developer.gnome.org/NetworkManager/stable/nmtui.html">nmtui</a> 工具。直接在终端中运行：</p>
<pre><code class="language-shell">nmtui
</code></pre>
<h2 id="安装无线网卡驱动">安装无线网卡驱动</h2>
<p>适用于博通BCM43xx无线网卡。</p>
<pre><code class="language-shell">sudo apt install bcmwl-kenrnel-source
</code></pre>
<h2 id="安装搜狗拼音输入法">安装搜狗拼音输入法</h2>
<p><a href="http://rangerzhou.top/2018/10/30/Ubuntu18.04_installation/">参考</a></p>
<pre><code class="language-shell"># 卸载ibus
sudo apt remove ibus
# 清除ibus配置
sudo apt purge ibus
# 卸载顶部面板任务栏上的键盘指示
sudo apt remove indicator-keyboard
# 安装fcitx输入法框架
sudo apt install fcitx-table-wbpy fcitx-config-gtk
# 切换为 Fcitx输入法
im-config -n fcitx
# im-config 配置需要重启系统才能生效
sudo shutdown -r now
# 下载安装包：https://pinyin.sogou.com/linux/?r=pinyin
# 安装搜狗输入法
sudo dpkg -i ~/Downloads/sogoupinyin_2.2.0.0108_amd64.deb
# 修复损坏缺少的包
sudo apt-get install -f
# 打开 Fcitx 输入法配置
fcitx-config-gtk3
# 点击 + 添加搜狗输入法，并把搜狗移动到顶端
</code></pre>
<h2 id="安装xrdp服务">安装xrdp服务</h2>
<p>这真是个大坑！要特别注意安装包的顺序问题。</p>
<ol>
<li>
<p>安装软件包。</p>
<pre><code class="language-bash">#先安装这个
sudo apt-get install tightvncserver
#再安装这个
sudo apt-get install xrdp、
#再重启一下xrdp服务
sudo /etc/init.d/xrdp restart
</code></pre>
</li>
<li>
<p>根据桌面环境进行设置。</p>
<p>根据具体的桌面环境，还需进行相应的操作。推荐从<a href="https://www.hiroom2.com/ubuntu/ubuntu-18-04-en/">这个网站</a>的<code>Remote desktop server</code>一项中根据自己的桌面环境进行选择。</p>
</li>
<li>
<p>xrdp无法成功开启的解决办法。</p>
<p>查看<code>/var/log/xrdp-sesman.log</code>文档：</p>
<pre><code class="language-bash">sudo nano /var/log/xrdp-sesman.log
</code></pre>
<p>如果文档中有类似<code>X server for display 10 startup timeout</code>和<code>another Xserver is already active on display 10</code>类似的日志，很大可能是安装包顺序的问题，解决办法就是卸了重新按顺序安装。</p>
<pre><code class="language-bash">apt-get purge tightvnc xrdp
</code></pre>
<p>然后按照第一步的顺序安装。也可只卸载重装xrdp包（反正我是这么解决的）。</p>
<p>这是我遇到的唯一问题！</p>
</li>
</ol>
<h2 id="安装petalinuxxilinx">安装Petalinux(Xilinx)</h2>
<p><strong>注意</strong>：不能使用root权限来安装。</p>
<ol>
<li>
<p>报错<code>awk: read error (Bad address)</code>,参考<a href="https://blog.lazy-evaluation.net/posts/linux/petalinux-v2019.1-ubuntu-18.04.html">这篇</a>,只许安装<code>gawk</code>:</p>
<pre><code>sudo apt install gawk
</code></pre>
</li>
<li>
<p>报错<code>tar: .: Cannot change mode to rwxr-xr-x: Operation not permitted</code>这种类似错误，参考<a href="https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-2017-2-installation-failure/td-p/799769">这里</a>，需要修改文件的拥有用户：</p>
<pre><code class="language-shell">#例如安装在/opt/Xilinx/Petalinux/2018.3,<owner>为非root用户名，可使用echo $USER查看
sudo chown -R <owner>:<owner> /opt/Xilinx/Petalinux/2018.3
</code></pre>
</li>
</ol>
]]></content>
</entry>
<entry>
<title type="html"><![CDATA[数字电路时序初步及最小时钟周期计算]]></title>
<id>https://halftop.github.io/post/STA_junior</id>
<link href="https://halftop.github.io/post/STA_junior">
</link>
<updated>2019-07-12T08:27:11.000Z</updated>
<summary type="html"><![CDATA[<h2 id="几个时间概念">几个时间概念</h2>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>c</mi><mi>l</mi><mi>k</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{clk}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">c</span><span class="mord mathdefault mtight" style="margin-right:0.01968em;">l</span><span class="mord mathdefault mtight" style="margin-right:0.03148em;">k</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span>:时钟周期。两个时钟上升沿之间的时间。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>c</mi><mi>o</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{co}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.151392em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">c</span><span class="mord mathdefault mtight">o</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span> / <span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>c</mi><mi>t</mi><mi>o</mi><mi>q</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{ctoq}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.969438em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">c</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">o</span><span class="mord mathdefault mtight" style="margin-right:0.03588em;">q</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span></span></span></span>:寄存器更新延迟。clock output delay，时钟触发到数据输出的最大延迟时间。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>g</mi><mi>a</mi><mi>t</mi><mi>e</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{gate}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.969438em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight" style="margin-right:0.03588em;">g</span><span class="mord mathdefault mtight">a</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">e</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span></span></span></span> / <span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>d</mi><mi>a</mi><mi>t</mi><mi>a</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{data}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">d</span><span class="mord mathdefault mtight">a</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">a</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span>:逻辑门的延迟。一般包括传播延迟。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>s</mi><mi>e</mi><mi>t</mi><mi>u</mi><mi>p</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{setup}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.969438em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">s</span><span class="mord mathdefault mtight">e</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">u</span><span class="mord mathdefault mtight">p</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span></span></span></span>:触发器的建立时间。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>h</mi><mi>o</mi><mi>l</mi><mi>d</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{hold}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">h</span><span class="mord mathdefault mtight">o</span><span class="mord mathdefault mtight" style="margin-right:0.01968em;">l</span><span class="mord mathdefault mtight">d</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span>:触发器的保持时间。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>s</mi><mi>k</mi><mi>e</mi><mi>w</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{skew}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">s</span><span class="mord mathdefault mtight" style="margin-right:0.03148em;">k</span><span class="mord mathdefault mtight">e</span><span class="mord mathdefault mtight" style="margin-right:0.02691em;">w</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span>:时钟偏移。同一时钟到达不同的触发器的时钟引脚经历的路径可能存在差异，造成他们的时钟上升沿不是同时出现的，这种偏差称为时钟偏移。通过使用时钟树综合工具可以有效地减少时钟偏移，但是不能消除时钟偏移。</p>
]]></summary>
<content type="html"><![CDATA[<h2 id="几个时间概念">几个时间概念</h2>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>c</mi><mi>l</mi><mi>k</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{clk}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">c</span><span class="mord mathdefault mtight" style="margin-right:0.01968em;">l</span><span class="mord mathdefault mtight" style="margin-right:0.03148em;">k</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span>:时钟周期。两个时钟上升沿之间的时间。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>c</mi><mi>o</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{co}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.151392em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">c</span><span class="mord mathdefault mtight">o</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span> / <span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>c</mi><mi>t</mi><mi>o</mi><mi>q</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{ctoq}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.969438em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">c</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">o</span><span class="mord mathdefault mtight" style="margin-right:0.03588em;">q</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span></span></span></span>:寄存器更新延迟。clock output delay，时钟触发到数据输出的最大延迟时间。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>g</mi><mi>a</mi><mi>t</mi><mi>e</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{gate}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.969438em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight" style="margin-right:0.03588em;">g</span><span class="mord mathdefault mtight">a</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">e</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span></span></span></span> / <span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>d</mi><mi>a</mi><mi>t</mi><mi>a</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{data}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">d</span><span class="mord mathdefault mtight">a</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">a</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span>:逻辑门的延迟。一般包括传播延迟。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>s</mi><mi>e</mi><mi>t</mi><mi>u</mi><mi>p</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{setup}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.969438em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">s</span><span class="mord mathdefault mtight">e</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">u</span><span class="mord mathdefault mtight">p</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span></span></span></span>:触发器的建立时间。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>h</mi><mi>o</mi><mi>l</mi><mi>d</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{hold}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">h</span><span class="mord mathdefault mtight">o</span><span class="mord mathdefault mtight" style="margin-right:0.01968em;">l</span><span class="mord mathdefault mtight">d</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span>:触发器的保持时间。</p>
<p><span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>s</mi><mi>k</mi><mi>e</mi><mi>w</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{skew}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">s</span><span class="mord mathdefault mtight" style="margin-right:0.03148em;">k</span><span class="mord mathdefault mtight">e</span><span class="mord mathdefault mtight" style="margin-right:0.02691em;">w</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span>:时钟偏移。同一时钟到达不同的触发器的时钟引脚经历的路径可能存在差异，造成他们的时钟上升沿不是同时出现的，这种偏差称为时钟偏移。通过使用时钟树综合工具可以有效地减少时钟偏移，但是不能消除时钟偏移。</p>
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<h2 id="最小时钟周期计算">最小时钟周期计算</h2>
<center>
<img src="https://i.loli.net/2019/07/16/5d2ddbd82792a69889.png" alt="示意图" title="示意图" width="">
</center>
<center>
<img src="https://i.loli.net/2019/07/17/5d2ee3b15b96224880.png" alt="时序图" title="时序图" width="">
</center>
<p>显然有：<span class="katex"><span class="katex-mathml"><math><semantics><mrow><mi>T</mi><mo>≧</mo><msub><mi>t</mi><mrow><mi>c</mi><mi>o</mi></mrow></msub><mo>+</mo><msub><mi>t</mi><mrow><mi>g</mi><mi>a</mi><mi>t</mi><mi>e</mi></mrow></msub><mo>+</mo><msub><mi>t</mi><mrow><mi>s</mi><mi>e</mi><mi>t</mi><mi>u</mi><mi>p</mi></mrow></msub><mo>−</mo><msub><mi>t</mi><mrow><mi>s</mi><mi>k</mi><mi>e</mi><mi>w</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T \geqq t_{co} + t_{gate} + t_{setup} - t_{skew}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:1.01166em;vertical-align:-0.25583em;"></span><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span><span class="mrel amsrm">≧</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span></span><span class="base"><span class="strut" style="height:0.76508em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.151392em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">c</span><span class="mord mathdefault mtight">o</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">+</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.9011879999999999em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight" style="margin-right:0.03588em;">g</span><span class="mord mathdefault mtight">a</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">e</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">+</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.9011879999999999em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">s</span><span class="mord mathdefault mtight">e</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">u</span><span class="mord mathdefault mtight">p</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">−</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.76508em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">s</span><span class="mord mathdefault mtight" style="margin-right:0.03148em;">k</span><span class="mord mathdefault mtight">e</span><span class="mord mathdefault mtight" style="margin-right:0.02691em;">w</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span></p>
<p>所以最小时钟周期有<span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>T</mi><mrow><mi>m</mi><mi>i</mi><mi>n</mi></mrow></msub><mo>=</mo><msub><mi>t</mi><mrow><mi>c</mi><mi>o</mi></mrow></msub><mo>+</mo><msub><mi>t</mi><mrow><mi>g</mi><mi>a</mi><mi>t</mi><mi>e</mi></mrow></msub><mo>+</mo><msub><mi>t</mi><mrow><mi>s</mi><mi>e</mi><mi>t</mi><mi>u</mi><mi>p</mi></mrow></msub><mo>−</mo><msub><mi>t</mi><mrow><mi>s</mi><mi>k</mi><mi>e</mi><mi>w</mi></mrow></msub></mrow><annotation encoding="application/x-tex">T_{min} = t_{co} + t_{gate} + t_{setup} - t_{skew}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.83333em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault" style="margin-right:0.13889em;">T</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.31166399999999994em;"><span style="top:-2.5500000000000003em;margin-left:-0.13889em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">m</span><span class="mord mathdefault mtight">i</span><span class="mord mathdefault mtight">n</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.2777777777777778em;"></span><span class="mrel">=</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span></span><span class="base"><span class="strut" style="height:0.76508em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.151392em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">c</span><span class="mord mathdefault mtight">o</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">+</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.9011879999999999em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight" style="margin-right:0.03588em;">g</span><span class="mord mathdefault mtight">a</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">e</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">+</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.9011879999999999em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathdefault">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.28055599999999997em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">s</span><span class="mord mathdefault mtight">e</span><span class="mord mathdefault mtight">t</span><span class="mord mathdefault mtight">u</span><span class="mord mathdefault mtight">p</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">−</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.76508em;vertical-align:-0.15em;"></span><span class="mord"><span class="mord mathdefault">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.33610799999999996em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mathdefault mtight">s</span><span class="mord mathdefault mtight" style="margin-right:0.03148em;">k</span><span class="mord mathdefault mtight">e</span><span class="mord mathdefault mtight" style="margin-right:0.02691em;">w</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.15em;"><span></span></span></span></span></span></span></span></span></span></p>
]]></content>
</entry>
<entry>
<title type="html"><![CDATA[SPI协议及其Verilog实现]]></title>
<id>https://halftop.github.io/post/Verilog_SPI</id>
<link href="https://halftop.github.io/post/Verilog_SPI">
</link>
<updated>2019-06-16T11:50:42.000Z</updated>
<summary type="html"><![CDATA[<h2 id="简介">简介</h2>
<p>SPI(Serial Peripheral Interface)是一个串行的同步传输协议，不同于Uart和IIC，没有起始位和结束位而是以时钟沿来同步和传输；不同于采用数据包的形式，数据可以连续不中断地传输。是一种一对多的传输协议。4线SPI是全双工的接口，而3线SPI是半双工接口，本篇采用更通用的4线SPI来介绍。</p>
]]></summary>
<content type="html"><![CDATA[<h2 id="简介">简介</h2>
<p>SPI(Serial Peripheral Interface)是一个串行的同步传输协议，不同于Uart和IIC，没有起始位和结束位而是以时钟沿来同步和传输；不同于采用数据包的形式，数据可以连续不中断地传输。是一种一对多的传输协议。4线SPI是全双工的接口，而3线SPI是半双工接口，本篇采用更通用的4线SPI来介绍。</p>
<!-- more -->
<h3 id="接口">接口</h3>
<p>SPI总线有4根逻辑信号线：</p>
<ul>
<li>
<p><strong>SLCLK</strong>:串行时钟（由主机产生）</p>
</li>
<li>
<p><strong>SS/CS(Slave Select/Chip Select)</strong>:片选信号（由主机产生），通常是一个低电平有效信号</p>
</li>
<li>
<p><strong>MOSI (Master Output<span class="katex"><span class="katex-mathml"><math><semantics><mrow><mo>→</mo></mrow><annotation encoding="application/x-tex">\to</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.36687em;vertical-align:0em;"></span><span class="mrel">→</span></span></span></span>Slave Input)</strong>:主机向从机的数据传输线</p>
</li>
<li>
<p><strong>MISO (Master Input<span class="katex"><span class="katex-mathml"><math><semantics><mrow><mo>←</mo></mrow><annotation encoding="application/x-tex">\leftarrow</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.36687em;vertical-align:0em;"></span><span class="mrel">←</span></span></span></span>Slave Output)</strong>:从机向主机的数据传输线</p>
</li>
</ul>
<h3 id="数据传输">数据传输</h3>
<p>要开始SPI通信，主机必须发送时钟信号，并通过使能CS信号选择从机。片选通常是低电平有效信号。因此，主机必须在该信号上发送逻辑0以选择从机。SPI是全双工接口，主机和从机可以分别通过MOSI和MISO线路同时发送数据。在SPI通信期间，数据的发送（串行移出到MOSI/SDO总线上）和接收（采样或读入总线(MISO/SDI)上的数据）同时进行。串行时钟沿同步数据的移位和采样。SPI接口允许灵活选择时钟的上升沿或下降沿来采样和/或移位数据。</p>
<h3 id="时钟极性和相位选择">时钟极性和相位选择</h3>
<p>主机除了要设置时钟频率，还要设置与数据传输相关的时钟极性和相位。大多数厂商都将这两个设置选项命名为<code>CPOL</code>和<code>CPHA</code>。</p>
<ul>
<li><code>CPOL</code>决定串行时钟极性。
<ul>
<li><code>CPOL=0</code>时钟在空闲时处于低电平，时钟的前沿是上升沿、后沿是下降沿。</li>
<li><code>CPOL=1</code>时钟在空闲时处于高电平，时钟的前沿是下降沿、后沿是上升沿。</li>
</ul>
</li>
<li><code>CPHA</code>
<ul>
<li><code>CPHA=0</code>时，发出数据的一边（ the "out" side）在前一时钟周期的后沿改变数据，同时接收数据的一方（ the "in" side ）在当前时钟周期的前沿捕获数据。<strong>注意</strong>：在第一个时钟周期，第一位数据必须在前沿到来之前出现在<code>MOSI</code>传输线上。</li>
<li><code>CPHA=1</code>时，发出数据的一边（ the "out" side）在当前时钟周期的前沿改变数据，同时接收数据的一方（ the "out" side）在同一时钟周期的后沿捕获数据。**注意：**在最后一个时钟周期，从机要在片选失效之前保持<code>MISO</code>线上的数据。</li>
</ul>
</li>
</ul>
<p>归纳起来如下图：</p>
<center>
<img src="https://i.loli.net/2019/06/16/5d064c76df71274228.png" alt="通过CPOL和CPHA选择SPI模式" title="通过CPOL和CPHA选择SPI模式" width="">
</center>
<p>以上内容参考：<a href="https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Interface">Serial Peripheral Interface</a>、<a href="https://mp.weixin.qq.com/s/7HSgQOTpefBn4EryOYZ1Lg">一文读懂 4 线 SPI</a></p>
<p>如需了解更多信息，请点击上方链接。</p>
<h2 id="verilogtb">Verilog&tb</h2>
<p><a href="https://github.com/halftop/Interface-Protocol-in-Verilog/tree/master/general_SPI/rtl">verilog</a></p>
<p><a href="https://github.com/halftop/Interface-Protocol-in-Verilog/tree/master/general_SPI/tb">tb</a></p>
]]></content>
</entry>
<entry>
<title type="html"><![CDATA[Uart的Verilog实现]]></title>
<id>https://halftop.github.io/post/Verilog-Uart</id>
<link href="https://halftop.github.io/post/Verilog-Uart">
</link>
<updated>2019-06-06T12:05:47.000Z</updated>
<summary type="html"><![CDATA[<h2 id="概述">概述</h2>
<p>Uart是个缩写，全称是通用异步收发传输器（Universal Asynchronous Receiver/Transmitter）。单向传输只需要单线。异步传输的意思是没有同步时钟来同步发送端和接受端的数据，所以在数据之前添加起始位，之后添加结束位，以此来判断传输过程的开始和结束。当接收端检测到开始位，即开始以特定的频率来接收输入的bit位，这个特定的频率称为波特率。发送端和接收端要在大致相同的波特率下工作，才可以保证传输的正确性（最多相差10%）。</p>
]]></summary>
<content type="html"><![CDATA[<h2 id="概述">概述</h2>
<p>Uart是个缩写，全称是通用异步收发传输器（Universal Asynchronous Receiver/Transmitter）。单向传输只需要单线。异步传输的意思是没有同步时钟来同步发送端和接受端的数据，所以在数据之前添加起始位，之后添加结束位，以此来判断传输过程的开始和结束。当接收端检测到开始位，即开始以特定的频率来接收输入的bit位，这个特定的频率称为波特率。发送端和接收端要在大致相同的波特率下工作，才可以保证传输的正确性（最多相差10%）。</p>
<!-- more -->
<h2 id="数据包的构成">数据包的构成</h2>
<p>Uart协议的传输数据被整合成数据包，每个数据包包含1位起始位，5-9位的数据位（具体决定于需求等因素），1位可选的奇偶校验位和1-2位的停止位。如下图所示：</p>
<center>
<img src="https://i.loli.net/2019/06/07/5cf9cb2f3c5cd16813.png" alt="Uart数据包的构成" title="Uart数据包的构成" width="400">
</center>
<h3 id="起始位start-bit">起始位（start bit）</h3>
<p>数据传输线空闲的时候保持高电平，当开始传输时，拉低一个时钟周期，这就是起始位。当接受端检测到数据线由高到低的变化时便开始以约定的波特率来接收上述的数据包。</p>
<h3 id="数据帧data-frame">数据帧（data frame）</h3>
<p>这是实际需要传输的数据。如果使用奇偶校验功能的话，可以传输5-8位的数据；如果不使用奇偶校验功能，则可以传输9位。一般由最低位开始传输。</p>
<h3 id="奇偶校验位parity">奇偶校验位（parity）</h3>
<p>用于接收端判断接收到的数据的正误。当接受端接收到数据帧后，计算其中1的个数是奇数个还是偶数个。如果奇偶校验位是0(偶校验)，那么数据帧中1的个数应该是一个偶数。如果奇偶校验位是1(奇校验)，那么数据帧中1的个数应该是奇数。当奇偶校验位与数据匹配时，传输没有错误。但是如果奇偶校验位是0，但1的个数是奇数或者奇偶校验位是1，个数却是偶数，则数据传输过程中发生了变化。奇偶校验只有粗略判断正误的功能，没有改正的能力。</p>
<h3 id="停止位stop-bits">停止位（stop bits）</h3>
<p>高电平保持1-2个时钟周期表示1-2位停止位，即停止位为高电平。</p>
<p>以上参考：<a href="http://www.circuitbasics.com/basics-uart-communication/">BASICS OF UART COMMUNICATION</a></p>
<h2 id="波特率">波特率</h2>
<h3 id="波特率和比特率">波特率和比特率</h3>
<p>比特率：每秒钟传输的二进制位数（bit），表示有效数据的传输速率，单位是b/s 、bit/s、比特/秒，读作：比特每秒。</p>
<p>波特率：波特率可以被理解为单位时间内传输符号的个数（传符号率），通过不同的调制方法可以在一个符号上负载多个比特信息。</p>
<p>比特率和波特率在数值上有如下关系：</p>
<p class='katex-block'><span class="katex-display"><span class="katex"><span class="katex-mathml"><math><semantics><mrow><mi>I</mi><mo>=</mo><mi>S</mi><mo>⋅</mo><msub><mi>log</mi><mo></mo><mn>2</mn></msub><mi>N</mi></mrow><annotation encoding="application/x-tex">I=S \cdot \log _{2} N
</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.68333em;vertical-align:0em;"></span><span class="mord mathdefault" style="margin-right:0.07847em;">I</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span><span class="mrel">=</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span></span><span class="base"><span class="strut" style="height:0.68333em;vertical-align:0em;"></span><span class="mord mathdefault" style="margin-right:0.05764em;">S</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">⋅</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.93858em;vertical-align:-0.24414em;"></span><span class="mop"><span class="mop">lo<span style="margin-right:0.01389em;">g</span></span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.20696799999999996em;"><span style="top:-2.4558600000000004em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mtight">2</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.24414em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.16666666666666666em;"></span><span class="mord mathdefault" style="margin-right:0.10903em;">N</span></span></span></span></span></p>
<p>其中 <em><strong>I</strong></em> 为传信率（比特率），<em><strong>S</strong></em> 为波特率，<em><strong>N</strong></em> 为每个符号负载的信息量，而<span class="katex"><span class="katex-mathml"><math><semantics><mrow><msub><mi>log</mi><mo></mo><mn>2</mn></msub><mi>N</mi></mrow><annotation encoding="application/x-tex">\log _{2} N</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.93858em;vertical-align:-0.24414em;"></span><span class="mop"><span class="mop">lo<span style="margin-right:0.01389em;">g</span></span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.20696799999999996em;"><span style="top:-2.4558600000000004em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mtight">2</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.24414em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.16666666666666666em;"></span><span class="mord mathdefault" style="margin-right:0.10903em;">N</span></span></span></span>以比特为单位。</p>
<p>以RS232为例，假设目前“<strong>波特率</strong>”为 9600， 则此RS232的比特率计算为</p>
<p class='katex-block'><span class="katex-display"><span class="katex"><span class="katex-mathml"><math><semantics><mrow><mi>I</mi><mo>=</mo><mi>S</mi><mo>⋅</mo><msub><mi>log</mi><mo></mo><mn>2</mn></msub><mi>N</mi><mo>=</mo><mn>9600</mn><mo>⋅</mo><msub><mi>log</mi><mo></mo><mn>2</mn></msub><mn>2</mn><mo>=</mo><mn>9600</mn><mi>b</mi><mi>i</mi><mi>t</mi><mi mathvariant="normal">/</mi><mi>s</mi></mrow><annotation encoding="application/x-tex">I=S \cdot \log _{2} N=9600 \cdot \log _{2} 2=9600 b i t / s
</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.68333em;vertical-align:0em;"></span><span class="mord mathdefault" style="margin-right:0.07847em;">I</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span><span class="mrel">=</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span></span><span class="base"><span class="strut" style="height:0.68333em;vertical-align:0em;"></span><span class="mord mathdefault" style="margin-right:0.05764em;">S</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">⋅</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.93858em;vertical-align:-0.24414em;"></span><span class="mop"><span class="mop">lo<span style="margin-right:0.01389em;">g</span></span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.20696799999999996em;"><span style="top:-2.4558600000000004em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mtight">2</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.24414em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.16666666666666666em;"></span><span class="mord mathdefault" style="margin-right:0.10903em;">N</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span><span class="mrel">=</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span></span><span class="base"><span class="strut" style="height:0.64444em;vertical-align:0em;"></span><span class="mord">9</span><span class="mord">6</span><span class="mord">0</span><span class="mord">0</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">⋅</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.93858em;vertical-align:-0.24414em;"></span><span class="mop"><span class="mop">lo<span style="margin-right:0.01389em;">g</span></span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.20696799999999996em;"><span style="top:-2.4558600000000004em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mtight">2</span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.24414em;"><span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.16666666666666666em;"></span><span class="mord">2</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span><span class="mrel">=</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span></span><span class="base"><span class="strut" style="height:1em;vertical-align:-0.25em;"></span><span class="mord">9</span><span class="mord">6</span><span class="mord">0</span><span class="mord">0</span><span class="mord mathdefault">b</span><span class="mord mathdefault">i</span><span class="mord mathdefault">t</span><span class="mord">/</span><span class="mord mathdefault">s</span></span></span></span></span></p>
<p>常有人把RS232之<em>N</em> 误以为是每个“<strong>符号</strong>”（symbol）所夹带的讯息量为<span class="katex"><span class="katex-mathml"><math><semantics><mrow><msup><mn>2</mn><mn>8</mn></msup></mrow><annotation encoding="application/x-tex">2^8</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.8141079999999999em;vertical-align:0em;"></span><span class="mord"><span class="mord">2</span><span class="msupsub"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.8141079999999999em;"><span style="top:-3.063em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight">8</span></span></span></span></span></span></span></span></span></span></span>，但实际上每一个“<strong>位元</strong>”（bit）即为一个“<strong>符号</strong>”（symbol）。</p>
<p>计算机通信中，波特率与比特率虽在数值上相等，但是它们的意义并不相同。</p>
<p>以上参考：<a href="https://zh.wikipedia.org/wiki/%E6%B3%A2%E7%89%B9%E7%8E%87">波特率</a></p>
<h3 id="常见波特率">常见波特率</h3>
<p>9600、19200 、38400 、57600 、115200、230400、460800、921600</p>
<h3 id="时钟与波特率的计算">时钟与波特率的计算</h3>
<p>FPGA 主频如果为50M，则时钟周期就是20ns。若数据发送速率为9600bps，则一位数据需要的时间为1000000000/9600=104167ns，则FPGA 传送一位需要翻转104167/20=5208个周期才可传送一位，所以程序中需计数5208才可满足9600bps。</p>
<p>简单一点就是 <em><strong>时钟频率除以波特率</strong></em> 就是需要的计数。</p>
<h2 id="verilog模块详解">Verilog模块详解</h2>
<p><a href="https://github.com/halftop/Interface-Protocol-in-Verilog/tree/master/general_uart">全部rtl和tb</a></p>
<p><a href="https://www.cnblogs.com/xiaomeige/p/6390246.html">参考链接</a>，建议固定位宽和不需要奇偶校验，使用此博文中的简洁描述</p>
<h3 id="tx_clk_genv">tx_clk_gen.v</h3>
<p>发送波特率生成模块，在<code>tx_start</code>和<code>tx_done</code>两信号有效的间隙生成选择的波特率时钟信号。思路如上一节所述！</p>
<p>支持的波特率：9600、19200 、38400 、57600 、115200、230400、460800、921600，可由参数配置。</p>
<p>相应Verilog描述：</p>
<pre><code class="language-verilog">`timescale 1ns / 1ps
module tx_clk_gen
#(
parameter CLK_FREQUENCE = 50_000_000, //hz
BAUD_RATE = 9600 //9600、19200 、38400 、57600 、115200、230400、460800、921600
)
(
input clk , //system_clk
input rst_n , //system_reset
input tx_done , //once_tx_done
input tx_start , //once_tx_start
output reg bps_clk //baud_rate_clk
);
localparam BPS_CNT = CLK_FREQUENCE/BAUD_RATE-1,
BPS_WD = log2(BPS_CNT);
reg [BPS_WD-1:0] count;
reg c_state;
reg n_state;
//FSM-1 1'b0:IDLE 1'b1:send_data
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
c_state <= 1'b0;
else
c_state <= n_state;
end
//FSM-2
always @(*) begin
case (c_state)
1'b0: n_state = tx_start ? 1'b1 : 1'b0;
1'b1: n_state = tx_done ? 1'b0 : 1'b1;
default: n_state = 1'b0;
endcase
end
//FSM-3 FSM's output(count_en) is equal to c_state
//baud_rate_clk_counter
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
count <= {BPS_WD{1'b0}};
else if (!c_state)
count <= {BPS_WD{1'b0}};
else begin
if (count == BPS_CNT)
count <= {BPS_WD{1'b0}};
else
count <= count + 1'b1;
end
end
//baud_rate_clk_output
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
bps_clk <= 1'b0;
else if (count == 'd1)
bps_clk <= 1'b1;
else
bps_clk <= 1'b0;
end
//get_the_width_of_
function integer log2(input integer v);
begin
log2=0;
while(v>>log2)
log2=log2+1;
end
endfunction
endmodule
</code></pre>
<h3 id="uart_frame_txv">uart_frame_tx.v</h3>
<p>数据帧发送模块，支持通过参数设定波特率、奇偶检验位及数据位宽。采用状态机和移位寄存器实现。当有校验位时则发送检验位；若没有校验位则直接发送停止位（发送两次停止位），如下所示。</p>
<pre><code class="language-verilog">`timescale 1ns / 1ps
module uart_frame_tx
#(
parameter CLK_FREQUENCE = 50_000_000, //hz
BAUD_RATE = 9600 , //9600、19200 、38400 、57600 、115200、230400、460800、921600
PARITY = "NONE" , //"NONE","EVEN","ODD"
FRAME_WD = 8 //if PARITY="NONE",it can be 5~9;else 5~8
)
(
input clk , //system_clk
input rst_n , //system_reset
input frame_en , //once_tx_start
input [FRAME_WD-1:0] data_frame , //data_to_tx
output reg tx_done , //once_tx_done
output reg uart_tx //uart_tx_data
);
wire bps_clk;
tx_clk_gen
#(
.CLK_FREQUENCE (CLK_FREQUENCE), //hz
.BAUD_RATE (BAUD_RATE ) //9600、19200 、38400 、57600 、115200、230400、460800、921600
)
tx_clk_gen_inst
(
.clk ( clk ), //system_clk
.rst_n ( rst_n ), //system_reset
.tx_done ( tx_done ), //once_tx_done
.tx_start ( frame_en ), //once_tx_start
.bps_clk ( bps_clk ) //baud_rate_clk
);
localparam IDLE = 6'b00_0000 ,
READY = 6'b00_0001 ,
START_BIT = 6'b00_0010 ,
SHIFT_PRO = 6'b00_0100 ,
PARITY_BIT = 6'b00_1000 ,
STOP_BIT = 6'b01_0000 ,
DONE = 6'b10_0000 ;
wire [1:0] verify_mode;
generate
if (PARITY == "ODD")
assign verify_mode = 2'b01;
else if (PARITY == "EVEN")
assign verify_mode = 2'b10;
else
assign verify_mode = 2'b00;
endgenerate
reg [FRAME_WD-1:0] data_reg ;
reg [log2(FRAME_WD-1)-1:0] cnt ;
reg parity_even ;
reg [5:0] cstate ;
reg [5:0] nstate ;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 'd0;
else if (cstate == SHIFT_PRO & bps_clk == 1'b1)
if (cnt == FRAME_WD-1)
cnt <= 'd0;
else
cnt <= cnt + 1'b1;
else
cnt <= cnt;
end
//FSM-1
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cstate <= IDLE;
else
cstate <= nstate;
end
//FSM-2
always @(*) begin
case (cstate)
IDLE : nstate = frame_en ? READY : IDLE ;
READY : nstate = (bps_clk == 1'b1) ? START_BIT : READY;
START_BIT : nstate = (bps_clk == 1'b1) ? SHIFT_PRO : START_BIT;
SHIFT_PRO : nstate = (cnt == FRAME_WD-1 & bps_clk == 1'b1) ? PARITY_BIT : SHIFT_PRO;
PARITY_BIT : nstate = (bps_clk == 1'b1) ? STOP_BIT : PARITY_BIT;
STOP_BIT : nstate = (bps_clk == 1'b1) ? DONE : STOP_BIT;
DONE : nstate = IDLE;
default : nstate = IDLE;
endcase
end
//FSM-3
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_reg <= 'd0;
uart_tx <= 1'b1;
tx_done <= 1'b0;
parity_even <= 1'b0;
end else begin
case (nstate)
IDLE : begin
data_reg <= 'd0;
tx_done <= 1'b0;
uart_tx <= 1'b1;
end
READY : begin
data_reg <= 'd0;
tx_done <= 1'b0;
uart_tx <= 1'b1;
end
START_BIT : begin
data_reg <= data_frame;
parity_even <= ^data_frame; //生成偶校验位
uart_tx <= 1'b0;
tx_done <= 1'b0;
end
SHIFT_PRO : begin
if(bps_clk == 1'b1) begin
data_reg <= {1'b0,data_reg[FRAME_WD-1:1]};
uart_tx <= data_reg[0];
end else begin
data_reg <= data_reg;
uart_tx <= uart_tx;
end
tx_done <= 1'b0;
end
PARITY_BIT : begin
data_reg <= data_reg;
tx_done <= 1'b0;
case (verify_mode)
2'b00: uart_tx <= 1'b1; //若无校验多发一位STOP_BIT
2'b01: uart_tx <= ~parity_even;
2'b10: uart_tx <= parity_even;
default: uart_tx <= 1'b1;
endcase
end
STOP_BIT : uart_tx <= 1'b1;
DONE : tx_done <= 1'b1;
default : begin
data_reg <= 'd0;
uart_tx <= 1'b1;
tx_done <= 1'b0;
parity_even <= 1'b0;
end
endcase
end
end
function integer log2(input integer v);
begin
log2=0;
while(v>>log2)
log2=log2+1;
end
endfunction
endmodule
</code></pre>
<h3 id="uart_frame_rxv">uart_frame_rx.v</h3>
<p>数据接收模块的主要描述如下：</p>
<pre><code class="language-verilog">module uart_frame_rx
#(
parameter CLK_FREQUENCE = 50_000_000, //hz
BAUD_RATE = 9600 , //9600、19200 、38400 、57600 、115200、230400、460800、921600
PARITY = "NONE" , //"NONE","EVEN","ODD"
FRAME_WD = 8 //if PARITY="NONE",it can be 5~9;else 5~8
)
(
input clk , //sys_clk
input rst_n ,
input uart_rx ,
output reg [FRAME_WD-1:0] rx_frame , //frame_received,when rx_done = 1 it's valid
output reg rx_done , //once_rx_done
output reg frame_error //when the PARITY is enable if frame_error = 1,the frame received is wrong
);
wire sample_clk ;
wire frame_en ; //once_rx_start
reg cnt_en ; //sample_clk_cnt enable
reg [3:0] sample_clk_cnt ;
reg [log2(FRAME_WD+1)-1:0] sample_bit_cnt ;
wire baud_rate_clk ;
localparam IDLE = 5'b0_0000,
START_BIT = 5'b0_0001,
DATA_FRAME = 5'b0_0010,
PARITY_BIT = 5'b0_0100,
STOP_BIT = 5'b0_1000,
DONE = 5'b1_0000;
reg [4:0] cstate;
reg [4:0] nstate;
//
wire [1:0] verify_mode;
generate
if (PARITY == "ODD")
assign verify_mode = 2'b01;
else if (PARITY == "EVEN")
assign verify_mode = 2'b10;
else
assign verify_mode = 2'b00;
endgenerate
//detect the start condition--the negedge of uart_rx
reg uart_rx0,uart_rx1,uart_rx2,uart_rx3;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
uart_rx0 <= 1'b0;
uart_rx1 <= 1'b0;
uart_rx2 <= 1'b0;
uart_rx3 <= 1'b0;
end else begin
uart_rx0 <= uart_rx ;
uart_rx1 <= uart_rx0;
uart_rx2 <= uart_rx1;
uart_rx3 <= uart_rx2;
end
end
//negedge of uart_rx-----start_bit
assign frame_en = uart_rx3 & uart_rx2 & ~uart_rx1 & ~uart_rx0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt_en <= 1'b0;
else if (frame_en)
cnt_en <= 1'b1;
else if (rx_done)
cnt_en <= 1'b0;
else
cnt_en <= cnt_en;
end
assign baud_rate_clk = sample_clk & sample_clk_cnt == 4'd8;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
sample_clk_cnt <= 4'd0;
else if (cnt_en) begin
if (baud_rate_clk)
sample_clk_cnt <= 4'd0;
else if (sample_clk)
sample_clk_cnt <= sample_clk_cnt + 1'b1;
else
sample_clk_cnt <= sample_clk_cnt;
end else
sample_clk_cnt <= 4'd0;
end
//the start_bit is the first one (0),then the LSB of the data_frame is the second(1) ......
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
sample_bit_cnt <= 'd0;
else if (cstate == IDLE)
sample_bit_cnt <= 'd0;
else if (baud_rate_clk)
sample_bit_cnt <= sample_bit_cnt + 1'b1;
else
sample_bit_cnt <= sample_bit_cnt;
end
//read the readme
reg [1:0] sample_result ;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
sample_result <= 1'b0;
else if (sample_clk) begin
case (sample_clk_cnt)
4'd0:sample_result <= 2'd0;
4'd3,4'd4,4'd5: sample_result <= sample_result + uart_rx;
default: sample_result <= sample_result;
endcase
end
end
//FSM-1
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cstate <= IDLE;
else
cstate <= nstate;
end
//FSM-2
always @(*) begin
case (cstate)
IDLE : nstate = frame_en ? START_BIT : IDLE ;
START_BIT : nstate = (baud_rate_clk & sample_result[1] == 1'b0) ? DATA_FRAME : START_BIT ;
DATA_FRAME : begin
case (verify_mode[1]^verify_mode[0])
1'b1: nstate = (sample_bit_cnt == FRAME_WD & baud_rate_clk) ? PARITY_BIT : DATA_FRAME ; //parity is enable
1'b0: nstate = (sample_bit_cnt == FRAME_WD & baud_rate_clk) ? STOP_BIT : DATA_FRAME ; //parity is disable
default: nstate = (sample_bit_cnt == FRAME_WD & baud_rate_clk) ? STOP_BIT : DATA_FRAME ; //defasult is disable
endcase
end
PARITY_BIT : nstate = baud_rate_clk ? STOP_BIT : PARITY_BIT ;
STOP_BIT : nstate = (baud_rate_clk & sample_result[1] == 1'b1) ? DONE : STOP_BIT ;
DONE : nstate = IDLE;
default: nstate = IDLE;
endcase
end
//FSM-3
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rx_frame <= 'd0;
rx_done <= 1'b0;
frame_error <= 1'b0;
end else begin
case (nstate)
IDLE : begin
rx_frame <= 'd0;
rx_done <= 1'b0;
frame_error <= 1'b0;
end
START_BIT : begin
rx_frame <= 'd0;
rx_done <= 1'b0;
frame_error <= 1'b0;
end
DATA_FRAME : begin
if (sample_clk & sample_clk_cnt == 4'd6)
rx_frame <= {sample_result[1],rx_frame[FRAME_WD-1:1]};
else
rx_frame <= rx_frame;
rx_done <= 1'b0;
frame_error <= 1'b0;
end
PARITY_BIT : begin
rx_frame <= rx_frame;
rx_done <= 1'b0;
if (sample_clk_cnt == 4'd8)
frame_error <= ^rx_frame ^ sample_result[1];
else
frame_error <= frame_error;
end
STOP_BIT : begin
rx_frame <= rx_frame;
rx_done <= 1'b0;
frame_error <= frame_error;
end
DONE : begin
frame_error <= frame_error;
rx_done <= 1'b1;
rx_frame <= rx_frame;
end
default: begin
rx_frame <= rx_frame;
rx_done <= 1'b0;
frame_error <= frame_error;
end
endcase
end
end
rx_clk_gen
#(
.CLK_FREQUENCE (CLK_FREQUENCE ), //hz
.BAUD_RATE (BAUD_RATE ) //9600、19200 、38400 、57600 、115200、230400、460800、921600
)
rx_clk_gen_inst
(
.clk ( clk ) ,
.rst_n ( rst_n ) ,
.rx_start ( frame_en ) ,
.rx_done ( rx_done ) ,
.sample_clk ( sample_clk )
);
function integer log2(input integer v);
begin
log2=0;
while(v>>log2)
log2=log2+1;
end
endfunction
endmodule
</code></pre>
<p>根据uart协议，数据传输线空闲时位高电平，数据传输以一位低电平的起始位开始，因此准确检测起始位是数据成功传输的关键。由于接受端和发送端是异步的，需要专门的边沿检测电路来捕捉下降沿。这里采用4个移位寄存器，连续采集4个时钟上升沿时的数据，通过对比前两个时刻和后两个时刻的数据线的状态来得到数据线准确的下降沿，获得准确的开始接收条件。</p>
<p>在简单的串口接收中，我们通常选取一位数据的中间时刻进行采样，因为此时数据最稳定，但是在工业环境中，存在着各种干扰，在干扰存在的情况下，如果采用传统的中间时刻采样一次的方式，采样结果就有可能受到干扰而出错。为了滤除这种干扰，这里采用多次采样求概率的方式。如下图，将一位数据平均分成9个时间段，对位于中间的三个时间段进行采样。然后对三个采样结果进行统计判断，如果某种电平状态在三次采样结果中占到了两次及以上，则可以判定此电平状态即为正确的数据电平。例如4、5、6时刻采样结果分别为1、1、0，那么就取此位解码结果为1，否则，若三次采样结果为0、1、0，则解码结果就为0。即3次采样为a,b,c，则结果为<code>a&b | b&c |a&c</code>，显而易见此结果是全加器的进位，<a href="https://halftop.github.io/post/verilog99_12to21/#%E9%A2%98%E7%9B%AE012">参考链接</a>。</p>
<center>
<img src="https://i.loli.net/2019/06/11/5cffa2289f6cb31791.png" alt="数据采样示例" title="数据采样示例" width="600">
</center>
<h3 id="rx_clk_genv">rx_clk_gen.v</h3>
<p>所以采样时钟应该为波特率时钟的9倍，Verilog描述如下：</p>
<pre><code class="language-verilog">`timescale 1ns / 1ps
module rx_clk_gen
#(
parameter CLK_FREQUENCE = 50_000_000, //hz
BAUD_RATE = 9600 //9600、19200 、38400 、57600 、115200、230400、460800、921600
)
(
input clk ,
input rst_n ,
input rx_start ,
input rx_done ,
output reg sample_clk
);
localparam SMP_CLK_CNT = CLK_FREQUENCE/BAUD_RATE/9 - 1,
CNT_WIDTH = log2(SMP_CLK_CNT) ;
reg [CNT_WIDTH-1:0] clk_count ;
reg cstate;
reg nstate;
//FSM-1 1'b0:IDLE 1'b1:RECEIVE
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cstate <= 1'b0;
end else begin
cstate <= nstate;
end
end
//FSM-2
always @(*) begin
case (cstate)
1'b0: nstate = rx_start ? 1'b1 : 1'b0;
1'b1: nstate = rx_done ? 1'b0 : 1'b1 ;
default: nstate = 1'b0;
endcase
end
//FSM-3 FSM's output(clk_count_en) is equal to cstate
//sample_clk_counter
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
clk_count <= 'd0;
else if (!cstate)
clk_count <= 'd0;
else if (clk_count == SMP_CLK_CNT)
clk_count <= 'd0;
else
clk_count <= clk_count + 1'b1;
end
//generate sample_clk = 9xBAUD_RATE
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
sample_clk <= 1'b0;
else if (clk_count == 1'b1)
sample_clk <= 1'b1;
else
sample_clk <= 1'b0;
end
//get the width of sample_clk_counter
function integer log2(input integer v);
begin
log2=0;
while(v>>log2)
log2=log2+1;
end
endfunction
endmodule
</code></pre>
<h2 id="总结">总结</h2>
<p>顾及的功能太多，比如奇偶校验，位宽设定等，最终的描述不简洁。但是功能基本都实现了，把思路和代码沉淀在这里。Verilog和本文多处借鉴他人成果，都已给出参考链接，侵删。</p>
]]></content>
</entry>
<entry>
<title type="html"><![CDATA[Verilog99题-FIFO设计]]></title>
<id>https://halftop.github.io/post/verilog99_FIFO</id>
<link href="https://halftop.github.io/post/verilog99_FIFO">
</link>
<updated>2019-06-03T14:00:39.000Z</updated>
<summary type="html"><![CDATA[<h2 id="前言">前言</h2>
<p><a href="https://mp.weixin.qq.com/s/prdZKHbKTFMH80eRnr7mLQ">不忘出芯veriloig99题</a>的58-61题是关于FIFO设计，包括同步FIFO，异步FIFO和FIFO最小深度计算等问题。</p>
]]></summary>
<content type="html"><![CDATA[<h2 id="前言">前言</h2>
<p><a href="https://mp.weixin.qq.com/s/prdZKHbKTFMH80eRnr7mLQ">不忘出芯veriloig99题</a>的58-61题是关于FIFO设计，包括同步FIFO，异步FIFO和FIFO最小深度计算等问题。</p>
<!-- more -->
<h2 id="同步fifo设计">同步FIFO设计</h2>
<p>因为同步 FIFO 的读写速率是相同的，所以 FIFO 的大小设置不必考虑读写速率差和跨时钟域等问题，要简单很多。</p>
<blockquote>
<p>在 FIFO 内部，一般使用 dual port RAM 存储数据。双端口 RAM 有两套独立的读写地址，读地址和写地址分别由读指针和写指针来产生：写指针指向下一个数据被写入的地址，读指针指向下一个被读出的数据的地址，通过判断读写指针的相对大小，就可以得到 FIFO 的状态（full / empty）。</p>
</blockquote>
<blockquote>
<p>还有另外一种方法来产生 full / empty 信号：FIFO 内部维护一个计数器，每次写入一个数据 cnt++，每次读出一个数据 cnt--。这种方法产生 full / empty 很简单：当 cnt == 0，表示 FIFO empty；当 cnt == max，表示 FIFO full。虽然这种方法产生 full / empty 很简单，但是需要额外的计数器，而且计数器的位宽随着 FIFO 的深度增加，不仅占用的资源更多，而且会降低 FIFO 最终可以达到的速度。</p>
</blockquote>
<p>所以这里采用第一种方法实现。</p>
<h3 id="思路">思路</h3>
<p>调用34题的dual port SRAM来实现。</p>
<p>深度为<span class="katex"><span class="katex-mathml"><math><semantics><mrow><msup><mn>2</mn><mi>n</mi></msup></mrow><annotation encoding="application/x-tex">2^n</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.664392em;vertical-align:0em;"></span><span class="mord"><span class="mord">2</span><span class="msupsub"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.664392em;"><span style="top:-3.063em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mathdefault mtight">n</span></span></span></span></span></span></span></span></span></span></span>的FIFO，为读、写地址指针多添加一个额外的位。当写指针超过最后的FIFO地址时，写指针将使未使用的MSB（Most Significant Bit的缩写，指最高有效位）递增，同时将其余的位设置为零，如下图所示（FIFO已经回环并翻转指针的MSB位）。</p>
<center>
<img src="https://i.loli.net/2019/06/03/5cf52d50cb32615601.png" alt="空满状态判别" title="空满状态判别" width="700">
</center>
<p>读指针的操作与此类似，如果两个指针的MSB不同，则意味着写指针已经发生了回环。如果两个指针的MSB相同，则意味着两个指针都回环了相同的次数。</p>
<p>对于深度为<span class="katex"><span class="katex-mathml"><math><semantics><mrow><msup><mn>2</mn><mi>n</mi></msup></mrow><annotation encoding="application/x-tex">2^n</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.664392em;vertical-align:0em;"></span><span class="mord"><span class="mord">2</span><span class="msupsub"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.664392em;"><span style="top:-3.063em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mathdefault mtight">n</span></span></span></span></span></span></span></span></span></span></span>的FIFO，使用n位指针，其中（n-1）bit是访问整个FIFO存储器缓冲区所需的地址位数，当两个指针（包括MSB）相等时，FIFO为空；当两个指针（MSB除外）相等时，FIFO就会满。</p>
<center>
<img src="https://i.loli.net/2019/06/03/5cf53115e6ab143290.png" alt="FIFO的深度为8，需要用宽度为4的指针" title="FIFO的深度为8，我们需要用宽度为4的指针" width="">
</center>
<p>读写指针的关系就好比A,B两个田径运动员在一环形跑道上赛跑一样，当B运动员领先A并整整超前一圈时，A,B两人的地点相同，此种情况对应于读写指针指向了同一地址，但写指针超前整整一圈，FIFO被写满。和读空标志产生一样，写满标志也是读写指针相同时产生。但是如果地址的宽度和FIFO实际深度所需的宽度相等，某一时刻读写地址相同了，那FIFO是空还是满就难以判断了。所以读写指针需要增加一位来标记写地址是否超前读地址（在系统正确工作的前提下，读地址不可能超前于写地址），比如FIFO的深度为8，如上图所示需要用宽度为4的指针。</p>
<h3 id="verilog描述testbench">Verilog描述&testbench</h3>
<p><a href="https://github.com/halftop/code_of_Verilog_HDL99/blob/master/sources_1/new/test58.v">verilog</a></p>
<p><a href="https://github.com/halftop/code_of_Verilog_HDL99/blob/master/sim_1/new/tb58.v">testbench</a></p>
<p><a href="https://github.com/halftop/code_of_Verilog_HDL99/tree/master/sources_1/new/test_58_refrence">verilog_refrence</a></p>
<h3 id="参考链接">参考链接</h3>
<p><a href="http://guqian110.github.io/pages/2015/10/02/fifo_design_notes.html">FIFO 设计笔记</a></p>
<p><a href="http://www.sohu.com/a/114158723_458015">异步FIFO设计</a></p>
<h2 id="异步fifo设计">异步FIFO设计</h2>
<p>。。。。。。</p>
]]></content>
</entry>
<entry>
<title type="html"><![CDATA[Verilog99题-57题（单脉冲信号的跨时钟域传输）]]></title>
<id>https://halftop.github.io/post/verilog99-57</id>
<link href="https://halftop.github.io/post/verilog99-57">
</link>
<updated>2019-05-27T09:23:20.000Z</updated>
<summary type="html"><![CDATA[<h2 id="题目">题目</h2>
<blockquote>
<p>在clk a时钟域的一个单周期脉冲信号，如何正确的传递到clk b时钟域? 要考虑clk a和b的各种不同频率/相位的场景。</p>
</blockquote>
]]></summary>
<content type="html"><![CDATA[<h2 id="题目">题目</h2>
<blockquote>
<p>在clk a时钟域的一个单周期脉冲信号，如何正确的传递到clk b时钟域? 要考虑clk a和b的各种不同频率/相位的场景。</p>
</blockquote>
<!-- more -->
<h2 id="总结">总结</h2>
<p>关于单bit信号的跨时钟域传输<a href="https://www.cnblogs.com/IClearner/p/6485389.html">这篇博客</a>总结的比较详细，这里直接copy一下结论：</p>
<blockquote>
<ul>
<li>在跨时钟域的时候，不一定需要跨时钟域电路（同步器或者握手信号），接近异步时钟或者就是异步时钟的时候跨时钟域就得加上了。</li>
<li>在慢到快的时钟域中，加上触发器链（两级触发器）基本上就可以了，主要是抑制亚稳态的传播。</li>
<li>但是在快到慢的时钟域中，不仅需要触发器链进行抑制亚稳态的传播，还要防止慢时钟域采不到快时钟域的数据，因此就添加反馈/握手电路（这个反馈信号是指跨时钟域的反馈信号）。（可以使用脉冲展宽）</li>
</ul>
</blockquote>
<h2 id="verilog描述">Verilog描述</h2>
<p>参考了<a href="https://wx.zsxq.com/dweb/#/index/458811454428"><strong>NingHeChua*</strong></a>的描述</p>
<h3 id="慢时钟域到快时钟域两级寄存器同步">慢时钟域到快时钟域，两级寄存器同步</h3>
<pre><code class="language-verilog">module Sync_Pulse(
input clkb,
input rst_n,
input pulse_ina,
output pulse_outb
);
reg signal_r;
reg signal_rr;
always @ (posedge clkb or negedge rst_n)
if (!rst_n) begin
signal_r <= 1'b0;
signal_rr <= 1'b0;
end else begin
signal_r <= pulse_ina;
signal_rr <= signal_r;
end
assign pulse_outb = signal_rr;
endmodule
</code></pre>
<h3 id="快时钟域到慢时钟域">快时钟域到慢时钟域</h3>
<pre><code class="language-verilog">module Sync_Pulse(
input clka,
input clkb,
input rst_n,
input pulse_ina,
output pulse_outb,
output signal_outb
);
//-------------------------------------------------------
reg signal_a;
reg signal_b;
reg signal_b_r;
reg signal_b_rr;
reg signal_a_r;
reg signal_a_rr;
//-------------------------------------------------------
//在clka下，生成展宽信号signal_a
always @(posedge clka or negedge rst_n)begin
if(rst_n == 1'b0)begin
signal_a <= 1'b0;
end
else if(pulse_ina == 1'b1)begin
signal_a <= 1'b1;
end
else if(signal_a_rr == 1'b1)
signal_a <= 1'b0;
else
signal_a <= signal_a;
end
//-------------------------------------------------------
//在clkb下同步signal_a
always @(posedge clkb or negedge rst_n)begin
if(rst_n == 1'b0)begin
signal_b <= 1'b0;
end
else begin
signal_b <= signal_a;
end
end
//-------------------------------------------------------
//在clkb下生成脉冲信号和输出信号
always @(posedge clkb or negedge rst_n)begin
if(rst_n == 1'b0)begin
signal_b_r <= 'b0;
signal_b_rr <= 'b0;
end
else begin
signal_b_rr <= signal_b_r;
signal_b_r <= signal_b;
end
end
assign pulse_outb = ~signal_b_rr & signal_b_r;
assign signal_outb = signal_b_rr;
//-------------------------------------------------------
//在clka下采集signal_b_rr，生成signal_a_rr用于反馈拉低signal_a
always @(posedge clka or negedge rst_n)begin
if(rst_n == 1'b0)begin
signal_a_r <= 'b0;
signal_a_rr <= 'b0;
end
else begin
signal_a_rr <= signal_a_r;
signal_a_r <= signal_b_rr;
end
end
endmodule
</code></pre>
<center>
<img src="https://i.loli.net/2019/05/27/5cebb39c27a3271351.png" alt="rtl图" title="rtl图" width="800">
</center>
<p>补充一张采用与门、或门、非门、异或门、触发器实现的跨时钟域单bit信号传输的电路图，某发科2020年提前批招聘笔试就要求画出这张图。</p>
<center>
<img src="https://i.loli.net/2019/07/20/5d32d2ca826de68889.png" alt="某发科2020年提前批招聘笔试答案之一" title="某发科2020年提前批招聘笔试答案之一" width="">
</center>
<p>图中的“处理控制信号时长的逻辑”与本文中的“脉冲展宽”是同一概念。</p>
<p>本图转载自<a href="https://www.cnblogs.com/IClearner/p/6485389.html">这篇博客</a>。</p>
]]></content>
</entry>
<entry>
<title type="html"><![CDATA[AMBA-APB总线协议学习]]></title>
<id>https://halftop.github.io/post/amba-apb</id>