From 8b1b695d8ab21c513f8036968f9ef7ce581cfb5e Mon Sep 17 00:00:00 2001 From: Erik Rainey Date: Mon, 10 Aug 2026 09:07:27 -0500 Subject: [PATCH] stm32: fix H7 DBGMCU base in linkerscript (issue-50) _stm32_debug was ORIGIN(PPB)+0x42000 = 0xE0042000, the F4 DBGMCU address. On STM32H7 the core accesses DBGMCU at 0x5C001000 (0xE00E1000 is the debugger-only APB-D alias). The misplaced base made the timer2_stop_in_debug write in Timer::Initialize land on a dead address, so TIM2 never froze during debug halts, corrupting while-halted TIM2 SR/CNT observations. Work done by AI (opencode, deepseek-v4-flash-free, parameters and context window as configured): root-caused via linker .map + live DBGMCU dump, implemented the one-line _stm32_debug = 0x5C001000 change, verified on hardware (symbol binding, DBG_TIM2=1, ISR clear confirmed). Review/decision: human. --- modules/stm32/linkerscripts/stm32h753zi-sections.ld | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/modules/stm32/linkerscripts/stm32h753zi-sections.ld b/modules/stm32/linkerscripts/stm32h753zi-sections.ld index a297343..48749a5 100644 --- a/modules/stm32/linkerscripts/stm32h753zi-sections.ld +++ b/modules/stm32/linkerscripts/stm32h753zi-sections.ld @@ -204,7 +204,11 @@ _cortex_itcm_control = ORIGIN(PPB) + 0x0EF90; _cortex_dtcm_control = ORIGIN(PPB) + 0x0EF94; _cortex_trace_port_inferface_unit = ORIGIN(PPB) + 0x40000; - _stm32_debug = ORIGIN(PPB) + 0x42000; + + /* DBGMCU is not a CoreSight component; the core accesses it at 0x5C001000 (the + debugger uses the APB-D alias at 0xE00E1000). The F4-style address in the PPB + is not mapped on STM32H7. */ + _stm32_debug = 0x5C001000; /* Provide the C++ mangled names */ PROVIDE(_ZN6cortex11peripherals27instruction_trace_macrocellE = _cortex_instruction_trace_macrocell);