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author
Anton Schulte
committed
Fix Linter Messages
1 parent f44e97f commit a73d9e7

13 files changed

Lines changed: 28 additions & 42 deletions

vunit/library.py

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,12 @@
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"""
1212

1313
import logging
14-
from typing import cast
14+
from typing import cast, TYPE_CHECKING
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from vunit.design_unit import Entity, VHDLDesignUnit
16-
from typing import TYPE_CHECKING
16+
from vunit.vhdl_standard import VHDLStandard
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1818
if TYPE_CHECKING:
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from vunit.source_file import SourceFile, VHDLSourceFile, VerilogSourceFile
20-
from vunit.vhdl_standard import VHDLStandard
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LOGGER = logging.getLogger(__name__)
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vunit/project.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -515,7 +515,9 @@ def _get_files_to_recompile(self, files, dependency_graph, incremental):
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result_list.append(source_file)
516516
return result_list
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518-
def get_dependencies_in_compile_order(self, target_files=None, implementation_dependencies=False) -> list[SourceFile]:
518+
def get_dependencies_in_compile_order(
519+
self, target_files=None, implementation_dependencies=False
520+
) -> list[SourceFile]:
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"""
520522
Get a list of dependencies of target files including the
521523
target files.

vunit/sim_if/__init__.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,7 @@ def supports_coverage():
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"""
187187
return False
188188

189-
def merge_coverage(self, file_name, args): # pylint: disable=unused-argument
189+
def merge_coverage(self, file_name, args): # pylint: disable=unused-argument,no-self-use
190190
"""
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Hook for simulator interface to creating coverage reports
192192
"""

vunit/source_file.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,7 @@ def content_hash(self):
120120
return hash_string(self._content_hash + self._compile_options_hash())
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122122
def add_to_library(self, library: Library):
123-
raise NotImplemented
123+
raise NotImplementedError
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125125

126126
class VerilogSourceFile(SourceFile):

vunit/ui/__init__.py

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
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import logging
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import json
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import os
20-
from typing import Any, Callable, Literal, Optional, Set, Union, cast
20+
from typing import Any, Callable, Literal, Optional, Set, Union, cast, TYPE_CHECKING
2121
from pathlib import Path
2222
from fnmatch import fnmatch
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from vunit.test.list import TestList
@@ -47,7 +47,6 @@
4747
from .library import Library, LibraryList
4848
from .results import Results
4949

50-
from typing import TYPE_CHECKING
5150

5251
if TYPE_CHECKING:
5352
from vunit.source_file import SourceFile as Source_File

vunit/ui/common.py

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,10 +12,8 @@
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from glob import glob
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from os import environ
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from logging import getLogger
15-
from typing import Any, Iterable, Optional, List, TypeVar, Union
15+
from typing import Iterable, Optional, List, TypeVar, Union
1616

17-
from vunit.ui.source import SourceFile
18-
from ..sim_if import is_string_not_iterable
1917
from ..vhdl_standard import VHDL, VHDLStandard
2018

2119
LOGGER = getLogger(__name__)

vunit/ui/library.py

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,11 @@
1111
from pathlib import Path
1212
from fnmatch import fnmatch
1313
from typing import Any, List, Literal, Optional, Union
14-
from vunit.sim_if import OptionType
14+
from typing import TYPE_CHECKING
1515

16-
from vunit.test.bench_list import TestBenchList
17-
from vunit.ui.preprocessor import Preprocessor
16+
from ..sim_if import OptionType
17+
from ..test.bench_list import TestBenchList
18+
from .preprocessor import Preprocessor
1819
from ..vhdl_standard import VHDL, VHDLStandard
1920
from ..project import Project
2021
from ..source_file import file_type_of, FILE_TYPES, VERILOG_FILE_TYPES
@@ -24,8 +25,6 @@
2425
from .testbench import TestBench
2526
from .packagefacade import PackageFacade
2627

27-
from typing import TYPE_CHECKING
28-
2928
if TYPE_CHECKING:
3029
from vunit.ui import VUnit
3130

@@ -196,7 +195,7 @@ def add_source_files( # pylint: disable=too-many-arguments
196195
197196
"""
198197
return SourceFileList(
199-
source_files=[
198+
[
200199
self.add_source_file(
201200
file_name,
202201
preprocessors,
@@ -362,9 +361,6 @@ class LibraryList(List[Library]):
362361
A list of :class:`.Library`
363362
"""
364363

365-
def __init__(self, libraries: "list[Library]"):
366-
list.__init__(self, libraries)
367-
368364
def get_test_benches(self, pattern: str = "*", allow_empty: bool = False) -> list[TestBench]:
369365
"""
370366
Get a list of test benches

vunit/ui/packagefacade.py

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,11 @@
99
"""
1010

1111
from pathlib import Path
12-
from typing import Optional, Union
12+
from typing import Optional, Union, TYPE_CHECKING
1313
from vunit.design_unit import DesignUnit
1414

1515
from vunit.ui.source import SourceFileList
1616
from ..com import codec_generator
17-
from typing import TYPE_CHECKING
1817

1918
if TYPE_CHECKING:
2019
from vunit.ui import VUnit

vunit/ui/preprocessor.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ def __init__(self, order: int = 0) -> None:
2222
"""
2323
self.order = order
2424

25-
def run(self, code: str, file_name: str) -> str: # pylint: disable=unused-argument
25+
def run(self, code: str, file_name: str) -> str: # pylint: disable=unused-argument,no-self-use
2626
"""
2727
Preprocess code.
2828

vunit/ui/results.py

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,13 +9,12 @@
99
"""
1010

1111
from pathlib import Path
12-
from typing import Any, Dict, Optional, Union
13-
from typing import TYPE_CHECKING
12+
from typing import Any, Dict, Optional, Union, TYPE_CHECKING
13+
from .common import TEST_OUTPUT_PATH
1414

1515
if TYPE_CHECKING:
1616
from vunit.sim_if import SimulatorInterface
1717
from vunit.test.report import TestReport
18-
from .common import TEST_OUTPUT_PATH
1918

2019

2120
class Results(object):

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