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c-thalerc-thaler
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use single generic parameter
All generics are now integrated into a single parameter of type apb_master_t.
1 parent b3ce11b commit a3dd361

5 files changed

Lines changed: 270 additions & 20 deletions

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‎vunit/vhdl/verification_components/src/apb_master.vhd‎

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -16,22 +16,21 @@ use work.queue_pkg.all;
1616
use work.sync_pkg.all;
1717
use work.logger_pkg.all;
1818
use work.log_levels_pkg.all;
19+
use work.apb_master_pkg.all;
1920

2021
entity apb_master is
2122
generic (
22-
bus_handle : bus_master_t;
23-
drive_invalid : boolean := true;
24-
drive_invalid_val : std_logic := 'X'
23+
bus_handle : apb_master_t
2524
);
2625
port (
2726
clk : in std_logic;
2827
reset : in std_logic;
2928
psel_o : out std_logic;
3029
penable_o : out std_logic;
31-
paddr_o : out std_logic_vector(address_length(bus_handle) - 1 downto 0);
30+
paddr_o : out std_logic_vector(address_length(bus_handle.p_bus_handle) - 1 downto 0);
3231
pwrite_o : out std_logic;
33-
pwdata_o : out std_logic_vector(data_length(bus_handle) - 1 downto 0);
34-
prdata_i : in std_logic_vector(data_length(bus_handle) - 1 downto 0);
32+
pwdata_o : out std_logic_vector(data_length(bus_handle.p_bus_handle) - 1 downto 0);
33+
prdata_i : in std_logic_vector(data_length(bus_handle.p_bus_handle) - 1 downto 0);
3534
pready_i : in std_logic
3635
);
3736
end entity;
@@ -57,7 +56,7 @@ begin
5756
variable msg_type : msg_type_t;
5857
begin
5958
DISPATCH_LOOP : loop
60-
receive(net, bus_handle.p_actor, request_msg);
59+
receive(net, bus_handle.p_bus_handle.p_actor, request_msg);
6160
msg_type := message_type(request_msg);
6261

6362
if msg_type = bus_read_msg then
@@ -78,11 +77,11 @@ begin
7877
BUS_PROCESS: process
7978
procedure drive_bus_invalid is
8079
begin
81-
if drive_invalid then
82-
penable_o <= drive_invalid_val;
83-
paddr_o <= (paddr_o'range => drive_invalid_val);
84-
pwrite_o <= drive_invalid_val;
85-
pwdata_o <= (pwdata_o'range => drive_invalid_val);
80+
if bus_handle.p_drive_invalid then
81+
penable_o <= bus_handle.p_drive_invalid_val;
82+
paddr_o <= (paddr_o'range => bus_handle.p_drive_invalid_val);
83+
pwrite_o <= bus_handle.p_drive_invalid_val;
84+
pwdata_o <= (pwdata_o'range => bus_handle.p_drive_invalid_val);
8685
end if;
8786
end procedure;
8887

@@ -118,8 +117,8 @@ begin
118117
penable_o <= '1';
119118
wait until (pready_i and penable_o) = '1' and rising_edge(clk);
120119

121-
if is_visible(bus_handle.p_logger, debug) then
122-
debug(bus_handle.p_logger,
120+
if is_visible(bus_handle.p_bus_handle.p_logger, debug) then
121+
debug(bus_handle.p_bus_handle.p_logger,
123122
"Wrote 0x" & to_hstring(data_this_transaction) &
124123
" to address 0x" & to_hstring(addr_this_transaction));
125124
end if;

‎vunit/vhdl/verification_components/src/apb_master_pkg.vhd‎

Lines changed: 250 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,250 @@
1+
-- This Source Code Form is subject to the terms of the Mozilla Public
2+
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
3+
-- You can obtain one at http://mozilla.org/MPL/2.0/.
4+
--
5+
-- Copyright (c) 2014-2024, Lars Asplund lars.anders.asplund@gmail.com
6+
7+
library ieee;
8+
use ieee.std_logic_1164.all;
9+
use ieee.numeric_std.all;
10+
11+
use work.bus_master_pkg.all;
12+
use work.com_pkg.all;
13+
use work.com_types_pkg.all;
14+
use work.logger_pkg.all;
15+
use work.memory_pkg.memory_t;
16+
use work.memory_pkg.to_vc_interface;
17+
18+
package apb_master_pkg is
19+
20+
type apb_master_t is record
21+
-- Private
22+
p_bus_handle : bus_master_t;
23+
p_drive_invalid : boolean;
24+
p_drive_invalid_val : std_logic;
25+
p_ready_high_probability : real range 0.0 to 1.0;
26+
end record;
27+
28+
impure function new_apb_master(
29+
data_length : natural;
30+
address_length : natural;
31+
logger : logger_t := bus_logger;
32+
actor : actor_t := null_actor;
33+
drive_invalid : boolean := true;
34+
drive_invalid_val : std_logic := 'X';
35+
ready_high_probability : real := 1.0
36+
) return apb_master_t;
37+
38+
function get_logger(bus_handle : apb_master_t) return logger_t;
39+
40+
-- Blocking: Write the bus
41+
procedure write_bus(signal net : inout network_t;
42+
constant bus_handle : apb_master_t;
43+
constant address : std_logic_vector;
44+
constant data : std_logic_vector;
45+
-- default byte enable is all bytes
46+
constant byte_enable : std_logic_vector := "");
47+
procedure write_bus(signal net : inout network_t;
48+
constant bus_handle : apb_master_t;
49+
constant address : natural;
50+
constant data : std_logic_vector;
51+
-- default byte enable is all bytes
52+
constant byte_enable : std_logic_vector := "");
53+
54+
procedure wait_until_idle(signal net : inout network_t;
55+
bus_handle : apb_master_t);
56+
57+
-- Non blocking: Read the bus returning a reference to the future reply
58+
procedure read_bus(signal net : inout network_t;
59+
constant bus_handle : apb_master_t;
60+
constant address : std_logic_vector;
61+
variable reference : inout bus_reference_t);
62+
63+
procedure read_bus(signal net : inout network_t;
64+
constant bus_handle : apb_master_t;
65+
constant address : natural;
66+
variable reference : inout bus_reference_t);
67+
68+
-- Blocking: read bus with immediate reply
69+
procedure read_bus(signal net : inout network_t;
70+
constant bus_handle : apb_master_t;
71+
constant address : std_logic_vector;
72+
variable data : inout std_logic_vector);
73+
74+
procedure read_bus(signal net : inout network_t;
75+
constant bus_handle : apb_master_t;
76+
constant address : natural;
77+
variable data : inout std_logic_vector);
78+
79+
-- Blocking: Read bus and check result against expected data
80+
procedure check_bus(signal net : inout network_t;
81+
constant bus_handle : apb_master_t;
82+
constant address : std_logic_vector;
83+
constant expected : std_logic_vector;
84+
constant msg : string := "");
85+
86+
procedure check_bus(signal net : inout network_t;
87+
constant bus_handle : apb_master_t;
88+
constant address : natural;
89+
constant expected : std_logic_vector;
90+
constant msg : string := "");
91+
92+
-- Blocking: Wait until a read from address equals the value using
93+
-- std_match If timeout is reached error with msg
94+
procedure wait_until_read_equals(
95+
signal net : inout network_t;
96+
bus_handle : apb_master_t;
97+
addr : std_logic_vector;
98+
value : std_logic_vector;
99+
timeout : delay_length := delay_length'high;
100+
msg : string := "");
101+
102+
-- Blocking: Wait until a read from address has the bit with this
103+
-- index set to value If timeout is reached error with msg
104+
procedure wait_until_read_bit_equals(
105+
signal net : inout network_t;
106+
bus_handle : apb_master_t;
107+
addr : std_logic_vector;
108+
idx : natural;
109+
value : std_logic;
110+
timeout : delay_length := delay_length'high;
111+
msg : string := "");
112+
end package;
113+
114+
package body apb_master_pkg is
115+
116+
impure function new_apb_master(
117+
data_length : natural;
118+
address_length : natural;
119+
logger : logger_t := bus_logger;
120+
actor : actor_t := null_actor;
121+
drive_invalid : boolean := true;
122+
drive_invalid_val : std_logic := 'X';
123+
ready_high_probability : real := 1.0
124+
) return apb_master_t is
125+
variable bus_handle : bus_master_t := new_bus(
126+
data_length => data_length,
127+
address_length => address_length,
128+
logger => logger,
129+
actor => actor
130+
);
131+
begin
132+
return (
133+
p_bus_handle => bus_handle,
134+
p_drive_invalid => drive_invalid,
135+
p_drive_invalid_val => drive_invalid_val,
136+
p_ready_high_probability => ready_high_probability
137+
);
138+
end;
139+
140+
function get_logger(bus_handle : apb_master_t) return logger_t is
141+
begin
142+
return get_logger(bus_handle.p_bus_handle);
143+
end function;
144+
145+
-- Blocking: Write the bus
146+
procedure write_bus(signal net : inout network_t;
147+
constant bus_handle : apb_master_t;
148+
constant address : std_logic_vector;
149+
constant data : std_logic_vector;
150+
-- default byte enable is all bytes
151+
constant byte_enable : std_logic_vector := "") is
152+
begin
153+
write_bus(net, bus_handle.p_bus_handle, address, data, byte_enable);
154+
end procedure;
155+
156+
procedure write_bus(signal net : inout network_t;
157+
constant bus_handle : apb_master_t;
158+
constant address : natural;
159+
constant data : std_logic_vector;
160+
-- default byte enable is all bytes
161+
constant byte_enable : std_logic_vector := "") is
162+
begin
163+
write_bus(net, bus_handle.p_bus_handle, address, data, byte_enable);
164+
end procedure;
165+
166+
procedure wait_until_idle(signal net : inout network_t;
167+
bus_handle : apb_master_t) is
168+
begin
169+
wait_until_idle(net, bus_handle.P_bus_handle);
170+
end procedure;
171+
172+
-- Blocking: read bus with immediate reply
173+
procedure read_bus(signal net : inout network_t;
174+
constant bus_handle : apb_master_t;
175+
constant address : std_logic_vector;
176+
variable data : inout std_logic_vector) is
177+
begin
178+
read_bus(net, bus_handle.p_bus_handle, address, data);
179+
end procedure;
180+
181+
procedure read_bus(signal net : inout network_t;
182+
constant bus_handle : apb_master_t;
183+
constant address : natural;
184+
variable data : inout std_logic_vector) is
185+
begin
186+
read_bus(net, bus_handle.p_bus_handle, address, data);
187+
end procedure;
188+
189+
procedure read_bus(signal net : inout network_t;
190+
constant bus_handle : apb_master_t;
191+
constant address : natural;
192+
variable reference : inout bus_reference_t) is
193+
begin
194+
read_bus(net, bus_handle.p_bus_handle, address, reference);
195+
end procedure;
196+
197+
procedure read_bus(signal net : inout network_t;
198+
constant bus_handle : apb_master_t;
199+
constant address : std_logic_vector;
200+
variable reference : inout bus_reference_t) is
201+
begin
202+
read_bus(net, bus_handle.p_bus_handle, address, reference);
203+
end procedure;
204+
205+
-- Blocking: Read bus and check result against expected data
206+
procedure check_bus(signal net : inout network_t;
207+
constant bus_handle : apb_master_t;
208+
constant address : std_logic_vector;
209+
constant expected : std_logic_vector;
210+
constant msg : string := "") is
211+
begin
212+
check_bus(net, bus_handle.p_bus_handle, address, expected, msg);
213+
end procedure;
214+
215+
procedure check_bus(signal net : inout network_t;
216+
constant bus_handle : apb_master_t;
217+
constant address : natural;
218+
constant expected : std_logic_vector;
219+
constant msg : string := "") is
220+
begin
221+
check_bus(net, bus_handle.p_bus_handle, address, expected, msg);
222+
end procedure;
223+
224+
-- Blocking: Wait until a read from address equals the value using
225+
-- std_match If timeout is reached error with msg
226+
procedure wait_until_read_equals(
227+
signal net : inout network_t;
228+
bus_handle : apb_master_t;
229+
addr : std_logic_vector;
230+
value : std_logic_vector;
231+
timeout : delay_length := delay_length'high;
232+
msg : string := "") is
233+
begin
234+
wait_until_read_equals(net, bus_handle.p_bus_handle, addr, value, timeout, msg);
235+
end procedure;
236+
237+
-- Blocking: Wait until a read from address has the bit with this
238+
-- index set to value If timeout is reached error with msg
239+
procedure wait_until_read_bit_equals(
240+
signal net : inout network_t;
241+
bus_handle : apb_master_t;
242+
addr : std_logic_vector;
243+
idx : natural;
244+
value : std_logic;
245+
timeout : delay_length := delay_length'high;
246+
msg : string := "") is
247+
begin
248+
wait_until_read_bit_equals(net, bus_handle.p_bus_handle, addr, idx, value, timeout, msg);
249+
end procedure;
250+
end package body;

‎vunit/vhdl/verification_components/src/apb_slave.vhd‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ library osvvm;
1212
use osvvm.RandomPkg.RandomPType;
1313

1414
use work.memory_pkg.all;
15-
use work.apb_pkg.all;
15+
use work.apb_slave_pkg.all;
1616
use work.logger_pkg.all;
1717

1818
entity apb_slave is

vunit/vhdl/verification_components/src/apb_pkg.vhd renamed to vunit/vhdl/verification_components/src/apb_slave_pkg.vhd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ use work.logger_pkg.all;
1414
use work.memory_pkg.memory_t;
1515
use work.memory_pkg.to_vc_interface;
1616

17-
package apb_pkg is
17+
package apb_slave_pkg is
1818

1919
type apb_slave_t is record
2020
ready_high_probability : real range 0.0 to 1.0;
@@ -35,7 +35,7 @@ package apb_pkg is
3535
constant slave_read_msg : msg_type_t := new_msg_type("apb slave read");
3636
end package;
3737

38-
package body apb_pkg is
38+
package body apb_slave_pkg is
3939

4040
impure function new_apb_slave(
4141
memory : memory_t;

‎vunit/vhdl/verification_components/test/tb_apb_master.vhd‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,8 @@ context work.vunit_context;
1212
context work.com_context;
1313
use work.memory_pkg.all;
1414
use work.bus_master_pkg.all;
15-
use work.apb_pkg.all;
15+
use work.apb_slave_pkg.all;
16+
use work.apb_master_pkg.all;
1617
use work.logger_pkg.all;
1718

1819
library osvvm;
@@ -39,8 +40,8 @@ architecture a of tb_apb_master is
3940
signal prdata : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
4041
signal pready : std_logic := '0';
4142

42-
constant bus_handle : bus_master_t := new_bus(data_length => pwdata'length,
43-
address_length => paddr'length);
43+
constant bus_handle : apb_master_t := new_apb_master(data_length => pwdata'length,
44+
address_length => paddr'length);
4445
constant memory : memory_t := new_memory;
4546
constant slave_handle : apb_slave_t := new_apb_slave(memory => memory,
4647
logger => get_logger("apb slave"),

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