fix whitespace issues

Author: c-thaler

vunit/vhdl/verification_components/src/apb_master.vhd

@@ -57,7 +57,7 @@ begin
   PROC_MAIN: process
     variable request_msg : msg_t;
     variable msg_type : msg_type_t;
-  begin    
+  begin
     DISPATCH_LOOP : loop
       receive(net, bus_handle.p_bus_handle.p_actor, request_msg);
       msg_type := message_type(request_msg);
@@ -133,16 +133,16 @@ begin
 
       elsif msg_type = bus_read_msg then
         addr_this_transaction := pop_std_ulogic_vector(request_msg);
-        
+
         psel_o <= '1';
         penable_o <= '0';
         pwrite_o <= '0';
         paddr_o <= addr_this_transaction;
-        
+
         wait until rising_edge(clk);
         penable_o <= '1';
         wait until (pready_i and penable_o) = '1' and rising_edge(clk);
-        
+
         reply_msg := new_msg;
         push_std_ulogic_vector(reply_msg, prdata_i);
         reply(net, request_msg, reply_msg);

vunit/vhdl/verification_components/src/apb_master_pkg.vhd

@@ -66,7 +66,7 @@ package apb_master_pkg is
                      constant bus_handle : apb_master_t;
                      constant address : std_logic_vector;
                      variable data : inout std_logic_vector);
-                     
+
   procedure read_bus(signal net : inout network_t;
                      constant bus_handle : apb_master_t;
                      constant address : natural;
@@ -78,7 +78,7 @@ package apb_master_pkg is
                       constant address : std_logic_vector;
                       constant expected : std_logic_vector;
                       constant msg : string := "");
-                      
+
   procedure check_bus(signal net : inout network_t;
                       constant bus_handle : apb_master_t;
                       constant address : natural;
@@ -225,7 +225,7 @@ package body apb_master_pkg is
   begin
     check_bus(net, bus_handle.p_bus_handle, address, expected, msg);
   end procedure;
-  
+
   -- Blocking: Wait until a read from address equals the value using
   -- std_match If timeout is reached error with msg
   procedure wait_until_read_equals(

vunit/vhdl/verification_components/src/apb_slave.vhd

@@ -33,7 +33,7 @@ entity apb_slave is
 end entity;
 
 architecture a of apb_slave is
-    
+
 begin
 
   PROC_MAIN: process
@@ -77,7 +77,7 @@ begin
 
       if penable_i = '0' then
         failure(bus_handle.p_logger, "penable_i must be active in the ACCESS phase.");
-      end if; 
+      end if;
     end loop;
   end process;
 

vunit/vhdl/verification_components/src/apb_slave_pkg.vhd

@@ -73,5 +73,4 @@ package body apb_slave_pkg is
       p_ready_high_probability => ready_high_probability
     );
   end;
-  
 end package body;

vunit/vhdl/verification_components/test/tb_apb_master.vhd

@@ -137,7 +137,7 @@ begin
 
   U_DUT_MASTER: entity work.apb_master
     generic map (
-      bus_handle => bus_handle 
+      bus_handle => bus_handle
     )
     port map (
       clk         => clk,
@@ -153,7 +153,7 @@ begin
 
   U_DUT_SLAVE: entity work.apb_slave
     generic map (
-      bus_handle  => slave_handle 
+      bus_handle  => slave_handle
     )
     port map (
       clk         => clk,