This is a follow up on [Release plan v1.0](https://github.com/VHDL/Interfaces/issues/6) for a future v1.x * [ ] Add contribution rules * [ ] Documentation * [x] Register https://vhdl-interfaces.rtfd.io/ * [x] Provide initial documentation skeleton - see #11 * [ ] Document naming rules from #10 in documentation * [ ] Add low-speed serial interfaces * [ ] QSPI * [ ] RS232 * [ ] Add low-speed parallel interfaces * [ ] LPT * [ ] ULPI * [ ] Video/Graphics * [ ] DVI - request #17 * [ ] HDMI - request #18 * [ ] DP - request #19 * [ ] LCD * [ ] Ethernet * [ ] XAUI * [ ] High Speed parallel interfaces * [ ] PCI * [ ] High Speed serial interfaces * [ ] PCI Express → #39 * [ ] Aurora * [ ] Interlaken * [ ] ARM AMBA * [ ] Trace (Mictor38 Trace Bus) * [x] Intel (Altera) * [x] Avalon-MM - request #24 → #37 * [x] Avalon-ST - request #25 → #37 * [ ] FOSSi * [x] Wishbone B.3 → #38 * [ ] Wishbone B.4 - request #23 * [ ] OSVVM * [ ] Streaming Model Independent Transaction Interface (Streaming MIT) * [ ] Address Bus Model Independent Transaction Interface (Address Bus MIT)
This is a follow up on Release plan v1.0 for a future v1.x
→ Feature/pcie #39
→ Feature/avalon #37
→ Feature/avalon #37
→ Feature/wishbone #38