From 37b06996109789003cf5a53787b8395be256efe1 Mon Sep 17 00:00:00 2001 From: Wonhyuk Yang Date: Tue, 21 Jul 2026 20:21:28 +0900 Subject: [PATCH] [Config] Add the missing dense-path keys to the heterogeneous config heterogeneous_c2_simple_noc.yml lacked pytorchsim_functional_mode, pytorchsim_timing_mode and core_spad_size_kb. These keys became mandatory for the dense (ws_mesh) path after the config was last touched, so the heterogeneous run in scripts/stonne_experiment/run.sh died with KeyError: 'pytorchsim_functional_mode' raised from extension_config.__getattr__ as soon as the dense matmul kernel was launched on the second partition. The sparse-only and dense-only modes were unaffected because they use other config files. Values match the systolic_ws_128x128_c1_simple_noc_tpuv3_half config; core_spad_size_kb is 16384, consistent with the 128 lanes x 128 KB per lane already declared here. With this, test_hetro.py --mode 2 completes in 48177 cycles. Co-Authored-By: Claude Opus 4.8 Claude-Session: https://claude.ai/code/session_01D3QZ8xomsrbs4SoA5wLQvJ --- configs/heterogeneous_c2_simple_noc.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/heterogeneous_c2_simple_noc.yml b/configs/heterogeneous_c2_simple_noc.yml index 8a3401fe..c9eff44c 100644 --- a/configs/heterogeneous_c2_simple_noc.yml +++ b/configs/heterogeneous_c2_simple_noc.yml @@ -8,11 +8,15 @@ core_stats_print_period_cycles: 10000 num_stonne_per_core: 8 num_stonne_port: 64 num_systolic_array_per_core: 2 +core_spad_size_kb: 16384 vpu_num_lanes: 128 vpu_spad_size_kb_per_lane: 128 vpu_vector_length_bits: 256 +pytorchsim_functional_mode: 1 +pytorchsim_timing_mode: 1 + dram_type: ramulator2 dram_freq_mhz: 940 dram_channels: 16